Pcie* Enumeration And Allocation; Pcie* Non-Transparent Bridge (Ntb); Table 8. Pcie* Port Routing - Cpu #2 - Penguin Computing Relion 1900e Technical Manual

Port 3C - x4
Port 3D -x4
CPU 2
PCI Ports
Port DMI 2/PCIe* x4 0
Port 1A - x4
Port 1B - x4
Port 2A - x4
Port 2B - x4
Port 2C - x4
Port 2D - x4
Port 3A - x4
Port 3B - x4
Port 3C - x4
Port 3D -x4
Note: See section 5.4.1 for details of root port to PCIe* slot mapping for each supported riser card.
5.2

PCIe* Enumeration and Allocation

The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local Bus
Specification, Revision 2.2. The bus number is incremented when the BIOS encounters a PCI-PCI bridge
device.
Scanning continues on the secondary side of the bridge until all subordinate buses are assigned numbers.
PCI bus number assignments may vary from boot to boot with varying presence of PCI devices with PCI-PCI
bridges.
If a bridge device with a single bus behind it is inserted into a PCI bus, all subsequent PCI bus numbers below
the current bus are increased by one. The bus assignments occur once, early in the BIOS boot process, and
never change during the pre-boot phase.
The BIOS resource manager assigns the PIC-mode interrupt for the devices that are accessed by the legacy
code. The BIOS ensures that the PCI BAR registers and the command registers for all devices are correctly set
up to match the behavior of the legacy BIOS after booting to a legacy OS. Legacy code cannot make any
assumption about the scan order of devices or the order in which resources are allocated to them
The BIOS automatically assigns IRQs to devices in the system for legacy compatibility. A method is not
provided to manually configure the IRQs for devices.
5.3

PCIe* Non-Transparent Bridge (NTB)

PCI express* Non-Transparent Bridge (NTB) acts as a gateway that enables high performance, low overhead
communication between two intelligent subsystems, the local and the remote subsystems. The NTB allows a
local processor to independently configure and control the local subsystem, provides isolation of the local
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Relion 1900e/2900e Manual
D3 F3
Table 8. PCIe* Port Routing – CPU #2
Device (D) Function (F) On-board Device
F0
D1 F1
D1 F0
D2 F0
D2 F1
D2 F2
D2 F3
D3 F0
D3 F1
D3 F2
D3 F3
Riser Slot #1
Riser Slot #1
Riser Slot #3
Riser Slot #1
Riser Slot #1
Riser Slot #2
Riser Slot #2
Riser Slot #2
Riser Slot #2
Riser Slot #3
Riser Slot #3
Riser Slot #2
Riser Slot #2
Revision 1.3