Cpu 68000 Pcb - Dräger Babylog 8000 Technical & Service Manual

Function description
10.3

CPU 68000 PCB

The CPU 68000 PCB comprises the following components: 68000 CPU, EPROM, RAM, time-keeper
RAM, address decoder, multi function peripheral (four 8-bit timers, RS 232 interface, 8-bit I/O port),
DTACK and bus error generator, watchdog, power-on reset, interrupt controller, bus controller, and bus
interface.
The CPU 68000 PCB is clocked with 8 MHz. If the "communication" conversion kit is installed, the clock
frequency is increased to 16 MHz.
Bus-Interface
Control-Bus
Adreß-Bus
Daten-Bus
Adreß-Bus
Seriell
Powerfail
Digital I/O
Status CPU
Fig. 16: Block diagram of the CPU 68000 PCB
Dräger Medical AG & Co. KGaA
Reset
Power-on-
Reset
Interrupt
Interrupt
Controller
Bus-
Controller
Optionsschalter
6173.3
16 MHz
Adress-
8 MHz
decoder
CPU 68000
EPROM
Co-
RAM
prozessor
Time
DTACK-,
Keeper
Bus-Error-
RAM
Generator
Watchdog
Multi
Function
Peripheral
Babylog 8000
12 MHz
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