Memory Mirroring - IBM x3650 M3 Installation And User Manual

Table 10. DIMM installation sequence for non-mirroring (normal) mode (continued)
Installed microprocessors
Microprocessor socket 2

Memory mirroring

Memory-mirroring mode replicates and stores data on two pairs of DIMMs within
two channels simultaneously. If a failure occurs, the memory controller switches
from the primary pair of memory DIMMs to the backup pair of DIMMs. To enable
memory mirroring through the Setup utility, select System Settings → Memory. For
details about enabling memory mirroring, see "Using the Setup utility" on page
158. When you use the memory mirroring feature, consider the following
information:
v When you use memory mirroring, you must install a pair of DIMMs at a time.
One DIMM must be in channel 0, and the mirroring DIMM must be in the same
connector in channel 1. The two DIMMs in each pair must be identical in size,
type, rank (single, dual, or quad), and organization. They do not have to be
identical in speed. The channels run at the speed of the slowest DIMM in any of
the channels. See Table 12 on page 120 for the DIMM connectors that are in each
pair.
v Channel 2, DIMM connectors 7, 8, 9, 16, 17, and 18 are not used in
memory-mirroring mode.
v The maximum available memory is reduced to half of the installed memory
when memory mirroring is enabled. For example, if you install 64 GB of
memory using RDIMMs, only 32 GB of addressable memory is available when
you use memory mirroring.
The following diagram shows the memory channel interface layout with the
DIMM installation sequence for mirroring mode. The numbers within the boxes
indicate the DIMM population sequence in pairs within the channels, and the
numbers next to the boxes indicate the DIMM connectors within the channels. For
example, the following illustration shows the first pair of DIMMs (indicated by
ones (1) inside the boxes) should be installed in DIMM connectors 1 on channel 0
and DIMM connector 2 on channel 1. DIMM connectors 3, 6, 9, 12, 15, and 18 on
channel 2 are not used in memory-mirroring mode.
1
1
Figure 122. Memory channel interface layout
The following table lists the DIMM connectors on each memory channel.
DIMM connector population sequence
Install the DIMMs in the following sequence: 12, 15, 18, 11,
14, 17, 10, 13, 16
2 3
CH0
3 2 1
CPU1
CH1
2 3
6 5 4
CH2
9 8 7
6 5
CH0
10
CPU2
QPI
5
6
CH1
13
CH2
16
Chapter 2. Installing optional devices
4
11 12
4
14 15
17 18
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