Active Memory Mirroring - IBM Power Systems E870 Technical Overview And Introduction

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Table 2-14 Power E880 system node bandwidth estimates
System node bandwidths
L1 (data) cache
L2 cache
L3 cache
Total Memory
PCIe Interconnect
Intra-node buses
(two system nodes)
PCIe Interconnect: Each POWER8 processor has 32 PCIe lanes running at 7.877 Gbps
full-duplex. The bandwidth formula is calculated as follows:
32 lanes * 4 processors * 7.877Gbps * 2 = 252.064 GBps
Rounding: The bandwidths listed here may appear slightly differently in other materials
due to rounding of some figures.
For the entire Power E880 system populated with four system nodes, the overall bandwidths
are shown in Table 2-15.
Table 2-15 Power E880 total bandwidth estimates
Total bandwidths
L1 (data) cache
L2 cache
L3 cache
Total Memory
PCIe Interconnect
Inter-node buses (four
system nodes)
Intra-node buses (four
system nodes)
Note: At the time of writing, the Power E880 supports only two system nodes per server.

2.3.5 Active Memory Mirroring

The Power E870 and Power E880 systems have the ability to provide mirroring of the
hypervisor code across multiple memory CDIMMs. If a CDIMM that contains the hypervisor
code develops an uncorrectable error, its mirrored partner will enable the system to continue
to operate uninterrupted.
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IBM Power Systems E870 and E880 Technical Overview and Introduction
Draft Document for Review October 14, 2014 10:19 am
Power E880
32 cores @ 4.350 GHz
6,682 GBps
6,682 GBps
8,909 GBps
922 GBps
252.064 GBps
922 GBps
Power E880
128 cores @ 4.350 GHz
26,726 GBps
26,726 GBps
35,635 GBps
3,688 GBps
1008.256 GBps
307 GBps
3,688 GBps