Philips HDRW720 Service Manual page 195

Circuit-, IC descriptions and list of abbreviations
AE_DATAI_DV Audio Encoder Input data (PCM) from
DVIO
AE_DATAO Audio Encoder Output data (PCM)
AE_WCLK Audio Encoder I2S word clock
AE_WCLK_DV Audio Encoder I2S word clock to DVIO
AE_WCLK_VSM Audio Encoder I2S word clock to VSM
ANA_WE Analogue write enable
ANA_WE_LV Analogue write enable Low Voltage
B_IN_VIP Video blue input to Video Input
Processor
B_OUT Video blue output from Host Decoder
B_OUT_B Filtered blue video output
BA Bank Address
BCLK_CTL_SERVIC
E Bitclock control Service Interface
BE_BCLK Basic Engine I2S bit clock
BE_BCLK_VSM Basic Engine I2S bit clock to VSM
BE_CPR Basic Engine Control Processor ready
to accept data
BE_DATA_RD Basic Engine Data read
BE_DATA_WR Basic Engine Data write
BE_FAN Basic Engine FAN
BE_FLAG Basic Engine error flag
BE_IRQN Basic Engine interrupt request
BE_LOADN Basic Engine LOAD(LOW active)
BE_RXD Basic Engine S2B received data
BE_SUR Basic Engine servo unit ready to
accept data (S2B)
BE_SYNC Basic Engine sector/abs time sync
BE_TXD Basic Engine S2B transmitted data
BE_V4 Basic Engine versatile input pin
BE_WCLK Basic Engine I2S word clock
C_IN Video Chrominance input
C_IN_VIP Chrominance input to Video Input
Processor
C_OUT Chrominance output from Host
Decoder
C_OUT_B Filtered Chrominance output
CAS Column Address strobe
CB_OUT(9:0) Chrominance Blue out
CLK4 SDRAM clock
CPUINT0 Control processor unit interrupt
CPUINT1 Control processor unit interrupt
CR_OUT(9:0) Chrominance Red out
CTS1P Clear to send (Service Interface)
CVBS_OUT Composite video output out of the
Host Decoder
CVBS_OUT_B Filtered Composite video output
CVBS_OUT_B_VIP Composite video output to Video Input
Processor(digital board video loop)
CVBS_Y_IN Composite video/Luminance input
CVBS_Y_IN_A Composite video/Luminance input to
Video Input Processor
CVBS_Y_IN_B Composite video/Luminance input to
Video Input Processor
CVBS_Y_IN_C Composite video/Luminance input to
Video Input Processor
D_ADDR(10:0) Address bus
D_DATA(29:0) Data bus
D_EMPRESS(15:0) SDRAM data input/output of
EMPRESS
D_PAR_D(7:0) Front-end parallel interface data
(record)
D_PAR_DVALID Front-end parallel interface data valid
D_PAR_REQ Front-end parallel interface request
D_PAR_STR Front-end parallel interface strobe
D_PAR_SYNC Front-end parallel interface sync
DV_IN_CLK Digital Video in clock from DVIO board
DV_IN_CLK Digital Video in data bus from DVIO
board
DV_IN_HS Digital Video in horizontal
synchronisation from DVIO board
DV_IN_VS Digital Video in vertical
synchronisation from DVIO board
HDRW720/0x, DVDR725H/0x
EMI_A(21:1) External Memory Interface Address
Bus(Host Decoder)
EMI_BE0N External Memory Interface Lower byte
enable(Host Decoder)
EMI_BE1N External Memory Interface Upper byte
enable(Host Decoder)
EMI_CAS0N External Memory Interface SDRAM
column address strobe(Host Decoder)
EMI_CE1N External Memory Interface VSM
Lower bank enable
EMI_CE2N External Memory Interface VSM
Higher bank enable
EMI_CE3N External Memory Interface flash IC's
enable
EMI_D(15:0) External Memory Interface Data
Bus(Host Decoder)
EMI_PROCCLK External Memory Interface Processor
Clock(Host Decoder)
EMI_RWN External Memory Interface Read/Write
control signal(Host Decoder)
EMI_WAIT External Memory Interface Wait state
request(Host Decoder)
EMPRESS_BOOT EMPRESS BOOT select input
EMPRESS_IRQN EMPRESS Interrupt request output
FLASH_OEN FLASH output enable control signal
G_IN_VIP Video green input to Video Input
Processor
G_OUT Video green output from Host Decoder
G_OUT_B Filtered green video output from Host
Decoder
GNDD Digital Ground
HD_M_AD(13:0) Host Decoder SDRAM address bus
HD_M_CASN Host Decoder SDRAM column
address strobe
HD_M_CLK Host Decoder SDRAM clock
HD_M_CS0N Host Decoder SDRAM chip select
HD_M_DQ(15:0) Host Decoder SDRAM data bus
HD_M_DQML Host Decoder SDRAM data mask
enable(Lower)
HD_M_DQMU Host Decoder SDRAM data mask
enable(Upper)
HD_M_RASN Host Decoder SDRAM row address
strobe
HD_M_WEN Host Decoder SDRAM write enable
HSOUT Horizontal synchronisation OUT
ION Inverted ON: Enable the power supply
for the digital board when LOW
IRESET_DIG Initialisation of the digital board, HIGH
when power ON
JTAG3_TCK JTAG Test Clock
JTAG3_TD_VIP_TO_
VEJTAG Transmitted Data Video Input
Processor to Video Encoder
JTAG3_TD_VSM_TO
_VIPJTAG Transmitted Data Versatile
Stream Manager to Video Input
Processor
JTAG3_TMS JTAG Test Mode Select
JTAG3_TRSTN JTAG Test part ResetN
LOAD_DVN LOAD Digital Video(LOW active)
MUTEN Mute enable
MUTEN_LV Mute enable Low Voltage
P_SCAN_YUV(7:0) Progressive Scan digital video bus
R_IN_VIP Video Red input to Video Input
Processor
R_OUT Video Red output from Host Decoder
R_OUT_B Filtered Red Video output from Host
Decoder
RAS Row Address Strobe
RESETN Reset Host Decoder
RESETN_BE System reset basic engine (buffered)
RESETN_DVIO System reset Digital Video Input
Output (buffered)
RESETN_VE System reset Video Encoder
ROMH_CEN Flash 2 chip enable
9. EN 195