Philips HDRW720 Service Manual page 181

Circuit-, IC descriptions and list of abbreviations
PACKAGE PIN #
SO–8
1
2
3
4
5
6
7
8
IC7703 ADV7196A, Digital Board 2.1 Chrysalis, Progressive Scan Video Encoder
FUNCTIONAL BLOCK DIAGRAM
Y0–Y9
TEST PATTERN
GENERATOR
Cr0–Cr9
Cb0–Cb9
CORRECTION
CLKIN
HORIZONTAL
SYNC
VERTICAL GENERATOR
SYNC
BLANKING
RESET
PACKAGE PIN DESCRIPTION
PIN SYMBOL
V
CC
PWRGD
PGDELAY
COMP
GATE(H)
GATE(L)
V
FB
GND
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
CHROMA
4:2:2
TO
AND
4:4:4
DELAY
(SSAF)
AND
GAMMA
CHROMA
4:2:2
TO
4:4:4
(SSAF)
TIMING
HDRW720/0x, DVDR725H/0x
Power supply input.
Open collector output goes low when V
must externally limit current into this pin to less than 20 mA.
External capacitor programs PWRGD low–to–high transition delay.
Error amp output. PWM comparator reference input. A capacitor to
LGND provides error amp compensation and Soft Start. Pulling pin
< 0.45 locks gate outputs to a zero percent duty cycle state.
High–side switch FET driver pin. Capable of delivering peak currents
of 1.5 A.
Low–side synchronous FET driver pin. Capable of delivering peak
currents of 1.5 A.
Error amplifier and PWM comparator input.
Power supply return.
ADV7196A
CGMS
MACROVISION
LUMA
SSAF
2 INTER-
POLATION
SYNC
GENERATOR
2
I C MPU
PORT
9.
FUNCTION
is out of regulation. User
FB
11-BIT+
SYNC
DAC
11-BIT
DAC
11-BIT
DAC
DAC CONTROL
BLOCK
EN 181
DAC A (Y)
DAC B
DAC C
V
REF
RESET
COMP