Philips HDRW720 Service Manual page 189

Circuit-, IC descriptions and list of abbreviations
Pin Functions
Pin Name Pin Number
SDRAM contro l
115, 114, 143-149,
MA [11..0]
132-137, 139-140,
MD [15..0]
MCLK
MCS
MRAS
MCAS
MWE
MLDQM
MUDQM1
CPU interface
RESCPU
SH/68K
PCLK
LDS/WRL
UDS/WRH
RW/RD
DTACK/WAIT
IPL[2..0]
IRQACK
PA23/CS
PA[22..1]
PD[15..0]1 6-12, 7-3, 207-202
Flash/ROM control
FOE5
FWE
Video signal
CSI
HSI1
Interrupt acknowledge is derived from the logical combination of the Function Code FC0, FC1, FC2 of 68EC000.
I/O
OA
111-113
I/O
121, 123-129
142 O
116 O
117 O
118 O
119 OW
120 OL
41 OU
58 OC
62 IC
199 O
197 I
198 I
196 I
201 O
19-17 OI
57 I
21 I
22-25,28-30,39-
IC
50,54-56
I/O
9O
60 OW
169 Ic
68 IH
HDRW720/0x, DVDR725H/0x
Function
ddress Bus to SDRAM
Data Bus to SDRAM
Clock to SDRAM
Chip Select to SDRAM
Row Address Strobe to SDRAM
Column Address Strobe to SDRAM
rite Enable to SDRAM
ower Data Input / Output Mask to SDRA M
pper Data Input / Output Mask to SDRA M
PU reset signal
PU Bus mode selection
Clock to CPU
68EC000 mode: Lower Data Strobe
SH mode: Low Write strobe
68EC000 mode: Upper Data Strobe
SH mode: High Write strobe
68EC000 mode: Read/Write strobe
SH mode: Read strobe
68EC000 mode: Data Transfer Acknowledge
SH mode: WAIT
nterrupt Privilege Level
68EC000 mode: interrupt acknowledge
SH mode: IRQOUT from CPU
68EC000 mode: Address pin 23
SH mode: Chip Select input
PU address bus (SH mode use UPA[21..1] only)
CPU data bus
Output Enable to Flash memory / ROM
rite Enable to Flash memory
omposite sync input
sync input
9. EN 189
†