IBM Series 1 User Manual page 182

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INTRODUCTION
Figure 6-1 is a block diagram of the customer DPC adapter
feature. This feature provides the end-user with a subset
of the processor I/O channel. The interface adheres to the
processor I/O channel architecture with an additional
throughput delay of approximately 2.5 microseconds.
The DPC adapter feature is designed to perform direct
program control functions only and can be configured to
accommodate four (4), eight (8), or sixteen (16) I/O device
addresses. It therefore, allows for interrupt vectoring for
up to 16 interrupting sources. All the
dev~ces
attached to
the DPC adapter share a common prepare field (interrupt
level and I-bit). The adapter has 75 lines including 18
data bos out (2 parity bits), 18 data bus in (2 parity
bits), 16 interrupt request in lines (when configured for 16
I/O device addresses), 3 function bits, 4 modifier bits, 4
I/O device address bits, and 12 control and response lines.
The data flow is always 16 bits without the parity option or
18 bits (including 2 parity bits) with the parity option.
Diagnostic capability is designed into the DPC adapter
feature card. This capability allows the user to send data
or con trol informa·tion froll the processo.r and nwrap" the
same information back to the processor from either the
adapter card or from an external I/O device.
The
DPe
adapter feature uses TTL non-isolated cable
drivers with a current capacity of 175 mAe This allows a
wide range of customer termination schemes.
Jumper pins are provided on the circuit card to select the
address domain of the adapter. The configuration must
include assignment of a device address with a range of
either 4, 8, or 16 contiguous addresses. A parity option is
also selected to be compatible with attached devices.
Interrupts can be masked o:ff during external diagnostic mode
by jumper selection.
customer DPC Adapter 6-1