IBM Series 1 User Manual page 223

Poll Mechanism. The operational sequence for polling has
~~~-me~~~-~~iI~ned
into it for eliminating the classical
test anJ set condition and for minimizing the effects of
metastability. Figures 2-17 and 2-18 show a typical poll
mechanism for non-burst cycle stealing
alid
interrupt
polling. A single device adapter is assumed.
The
two types of requests, cycle steal request
and
interrupt request# are shown on the left side of Figure
2-17. These requests, whose sources would be latches, are
presented to
the
interface
after
suitable gating. In the
case of an intprrupt request, the level bits previously
loaded
by
a Prepare command are decoded to present a request
on one of the request in bus lines.
The
active conditions of the poll
ID
bits are
detected
for cycle
steal and interrupt respectively.
Also, pallID
bits 1 through 4 are compared with the level bits to
determine if the requested lavel of interrupt matches the
level being polled.
Figure
~-18
shows
the
poll latches. The sample latches
on the left are the
key
to the poll mechanism. The active
condition
of the
poll In bits for cycle steal or interrupt
cause
the
respective sampling latches to sample the state
of
request and prevent further requests from influEncing the
decision to capture for that poll sequence. The designed
deskew
between
poll ID and poll activation gives
these
sample latches ample time to resolve metastability prior to
poll activation. Note that the two sampling latches are
'D'
triggers without
the
final output latch. Polarity holds
co u
1 d
be use d , but
t
his c
i
L" C U
it can not n e c e s sa r i I Y be
genera.lized tor use in a multiple device at.tachment where
cycle steal requests and interrupt requests would be
processed concurrently.
The two latches on the right side of the figure are
common logic in the poll mechanism and assume that cycle
steal and interrupt requests are not posted at the same
time~
This would be the case in a single device adapteL.
The poll decision latch is biased to propagate the poll in
the absence of a sampled request. In the absence of poll,
the
poll decision polarity hold follows
the
outputs of the
sample latches. By thp time poll is activated, all inputs
to
the
poll decision latch are stable, including the compare
of thE interrupting level. The decision to propagate or
capture is therefore made prior to the activation of poll.
When poll is activated, it holds the value of the poll
d~cision latch
and
gates the appropriate poll propagate or
return tag. If a decision to capture has been made, the
poll capture latch is also set at this time. A circuit is
provided to block requests-in until the cycle steal ot'"
interrupt service sequence is complete.
The figure also illustrates the use of resets to degate
tags and accomplish appropriate
res~tting.
Note that device
reset is not included in these resets since its action and
time of occurrance is different from the asynchronous
channel directed resets. Device reset is
d
DPC command and
cannot arbitrarily reset the cycle steal portion of the poll
mechanism and the service gate capture latch. This is
because once a cycle steal request has been presented to the
2-4:3
GA34-0033