IBM Series 1 User Manual page 58

c
c
o
Res~l Sequences Descriytion
1.
2.
3.
4.
5.
The effect that Halt or MCHK, system reset,
or
power-on
reset must have, has been discussed at
various points
throughout this chapter.
The Halt or
~CHK
and system reset tags, when occurring,
are active for 4.8 microseconds minimum as seen at the
device interface. Power on reset sequencing is
discussed in the sUbsequent section, "Electrical
Characteristics".
The
deactivation of device interface signals active at
the time of the reset must be performed within
200
nanoseconds as seen at the device interface.
The processors may have unpredictable values on the
address, data, and status busses during resets.
Therefore, resetting of registers must not depend on
the values of these busses.
For specific information concerning a reset sequence in
conjunction with another sequence, refer to the
description of the basic sequences
in
earlier portions
of this section.
Processor I/O Channel 2-4]