IBM Series 1 User Manual page 52

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Sequence Description
Refer
to Figure 2-14.
The processor initiated IPL sequence
is executed as follows:
,
.
The initiate 1PL line is
activated
at
the
processor
channel
output, along with status bus bit 0 or 1, as a
result of pressing the load key.
status bus bit 0
and
1
reflect
the
position
of
the
1PL
source switch,
primary or alternate, at the
time
the
load
key
was
pressed.
The
first
system
reset in the sequence is
also activated at this
time.
Initiate
1PL
and
the
status
bus
are held valid until the activation of the
1PL tag at the processor channel input after the
first
sytem reset is deactivated.
On the activation of the logical 'AND' of initiate
1PL
and system reset, the device must dc reset the IPL
tag within 200 ns, T1, as seen at the device interface.
On
activation
of
the
first system reset, the device
executes all other system reset functions.
Because
of
possible
Skew,
system
reset may lag initiate IPL and
the status bus at the device interface.
Therefore, the
IPL
tag
may
temporarily
become active at the device
interface prior to the first
system
reset.
However,
the
processor
channel
ignores the IPL tag during the
initial part of the sequence and does
not
examine
it
until the first system reset has been
activated.
In no case should the device use the
leading-edge
transition
of the first system reset.
This is because
the first system reset could also lead the initiate IPL
and status bus at the device interface.
The
first
system
reset
is deactivated after a time,
CT1#
of
4.8
microseconds
minimum
at
the
device
interface.
The
IPL
source device then activates the
IPL tag.
The time, T2, from the
deactivation
of
the
first
system
reset
to
the activation of the IPL tag
must be
greater
than
zero
as
seen
at
the
device
interface,
but
the
maximum time is device dependent.
This maximum time
should
be
kept
within
reasonable
limits, and generally this time should only depend upon
electronic rather than mechanical delays.
As a result
of
1PL
going
active_
initiate
IPL
is
deactivated.
The
status
bus
is
not
valid for the
primary/alternate selection portion of the IPL sequence
after the time when initiate IPL is deactivated.
Processor I/O Channel
2-37

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