IBM Series 1 User Manual page 44
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c
6.
7.
c
o
overlap
of
data
strobe
and
service
gate
is
100
nanoseconds minimum as seen at the device interface.
Upon deactivation of both service gate and data strobe,
the
device
deactivates
address
bus
bits 00-15, the
condition
code
in
bus,
the
cycle
byte
and
input
indicators
as
appropriate,
and
the
data bus (on an
input transfer).
These lines must be deactivated prior
to
the
drop
of
service
gate
return as seen at the
device interface.
The
device
deactivates service gate return.
The
permissible delay, T4, from the deactivation of service
gate
and
data
strobe
to the deactivation of service
gate return, is 3 microseconds maximum as seen
at
the
device
interface.
This
delay
is
for
attachment
convenience, but it is strongly
reco •• ended
that
the
delay
be held to a minimum.
All device action for the
transfer
must
be
completed
prior
to
dropping
the
service gate return.
The
total duration of the cycle steal service sequence
is
timed
out
by
the
channel
for
error
detection
purposes.
The
total duration is measured in the same
way as for
an
interrupt
service
sequence.
If
the
timeout
occurs, the channel activates the halt or
~CHK
line.
If
the
device
attachment
adheres
to
the
specified
times
over
which it has control, the total
duration of the cycle steal sequence viII be within the
channel timeout under normal operation.
The sequence described here applies to cycle steal
servicing
in
burst
mode
also.
However, there is an
additional consideration in burst mode as noted by
CT5
in
Figure 2-10.
Service gate for the next cycle steal
transfer
may
activate
immediately
at
the
device
interface
after
deactivation
of service gate return.
Therefore, the device does
not
directly
control
the
demanded
rate of servicing in burst mode.
(The device
does
control
this
demand
in
normal
cycle
steal
transfers
because one request corresponds to one cycle
steal service sequence.) In burst mode, the device
can
only
exert
minor
control over the demand made
by
the
channel by indirectly
controlling
delays
of
service
gate return activation and deactivation.
However, this
mechanism is generally not
recommended
because
there
are
attendent
risks
of
device
underrun and channel
timeout.
The recommended mechanism for burst
mode
is
buffering
for
a
size
of data equal to the length of
burst.
Processor I/O Channel
2-29
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