IBM Series 1 User Manual page 138

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Figure 4-4 is a state and timing diagram for possible
receive sequences. There are three entry points on the
right side of the diagram, "A", tlB", and
IIC".
All exits
from the basic sequences on the left of the diagram connect
to one of the entry points. A circle with 2, 4, or 6
denotes an interrupt with the appropriate condition code
wit h in the c i r cl e ;
n
I • A • (
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R)
II
den
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t e s in t err up
t
a c c e pt ( and
Read) by the processor; the envelopes of both normal and
overrun receive operations are shown on the diagram.
Figure 4-4 includes a table of timings for the various
device bit rates. TRO is the time of a receive operation
from initiation
by
the device to the posting of an
interrupt. It is nine bit times at the selected frequency.
At 9600 BPS, TRO is 0.936 ms; at 110 BPS, it is 81.9 ms. TR
is the m1n1mum time between receive operations and is two
bit times at the selected frequency, on the average. At
9600 BPS, TR is 0.208 ms on the average; at 110 BPS it is
18.2
IDS
on the average. Device clock jitter and drift
causes TR to vary, depending upon device characteristics.
For programming purposes, a value for TR of the average less
15 percent should account for most devices attached.
The basic sequences on Figure 4-4 start from point A
with a normal receive operation that ends with an attention
interrupt being posted. The top line depicts interrupt
acceptance dnd reading of the receive data register within
time TH. The second line depicts a delay in the interrupt
acceptance and reading beyond time TR
OL
the initiation of
another receive operation
by
the device if the device is not
transmitting at rated speed. In this case, although the
receive data register can be read, the adapter has committed
to an overrun receive operation; this results in an
exception interrupt (condition code 2) when the current
operation is completed. A Read command is not necessary
following the acceptance of condition code 2. The extension
of lines 2 and 3 depicts two other possibilities following a
cond i tion code 2;
(1)
the in terr upt is accepted and the
receive data register is read within time TB, leading to
condition code 4, and (2) another delay in interrupt
acceptance, leading to another condition code 2.
Line 4 depicts a case of a very long delay in interrupt
acceptance and reading, leading to condition code 6. The
extension of lines 4, 5, 6, and 7 show other possibilities
following a condition code 6.
Note that some connections of basic sequences to entry
points on the timing diagram can result in sequences that
may be very long, depending upon the number of characters
transmitted from the device.
Teletypewriter Adapter 4-15