IBM Series 1 User Manual page 43

Refer to Figure 2-10. Cycle steal input and output
sequences are executed as follows:
1.
Service gate is activated. The device detecting the
first leading edge of the service gate activation
following a poll capture is the selected device for the
cycle steal service sequence. This is called service
gate capture.
2. Opon service gate capture, the device activates the
address bus, and if a byte transfer is to take place,
the cycle byte indicator. If the sequence is an input
transfer, the data bus and cycle input indicator are
also activated. These signals must be activated prior
to the activation of service gate return. They must be
held valid and must not change value until the
deactivation of service gate and data strobe measured
at the device interface.
3.
The permissible delay, T2, from service gate to
service gate return as seen at the device interface is
3 microseconds maximum. There is no specific timeout
on this delay. The delay is provided for convenience
only. However, it is strongly recommended that this
delay be held to a minimum for performance reasons.
The status bus (and the data bus on output sequences)
is activated by the channel.
4. Data strobe is activated. The duration of data strobe,
CT3, is 200 nanoseconds minimum as seen at the device
interface.
5.
2-28
As can be noted by the eelationship of CT1 and CT2
in Figure 2-10, the status and data busses may be valid
only just prioe to the activation of data strobe at the
device interface. Theeefoee, registration of status
and data with the leading edge of data strobe is not
eecommended unless delays are built into the attachment
to allow for trigger conditioning. Since parity must
be checked
by
the device on output sequences and error
status may be posted to the device on the status bus,
it should be noted that registration of data during
data strobe may necessitate double buffering.
If an error is posted to the device on the status
bus in a burst mode transfer (not the last transfer),
the device must complete one aore service sequence.
This additional transfer is a dummy cycle. No
device-beld parameters are to be updated nor are any
additional status bus bits to be accumulated.
Service gate and data strobe
are
deactivated
simultaneously at the processor channel output.
As
denoted by the relationship of CT3 and
CT4
in Figure
2-10, data strobe may extend beyond the active envelope
of service gate by 100 nanoseconds
maximum,
but
the
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