IBM Series 1 User Manual page 27

On
cycle steal service sequences, the condition code in
bus is used by the device to pass the
address key to the
channel. On cycle steal data transfers, condition code bits
0--2 are logically equal to the cycle steal address
key.
This key is bits 5--7 of the DCB control word previously
fetched by the device. During cycle steal transfers for
fetching the DeB and for reporting residual status, a value
of logical zero is used for the address key. During IPL
cycle steal transfers a value of logical zero is also used
for the address key.
£.Y.£1~
InE!!! IndicatQ!:. This is an inbound tag used
by
the
device on a cycle steal service sequence. This tag signals
the channel that the cycle steal is either: (1) an output
from storage or (2) an input to storage. When the indicator
is a logical 1, an input to storage is indicated. When the
indicator is a logical 0, an output from storage is
indicated.
Cycl~ ~~i~
Ingica!Q£. This is an inbound tag used by the
device on a cycle steal service sequence. This tag signals
the channel that the cycle steal is either: (1) a word
transfer or (2) a byte transfer. When the indicator is a
logical 1. a byte transfer is indicated. When the indicator
is a logical 0, a word transfer is indicated.
sta!.!!§ BU§.
This is an outbound 4-bit bus used by the
channel on a cycle steal service sequence. The bus signals
the device being serviced of any errors the channel has
detected. The bus is bit significant as follows:
status bus bit
o
1
2
3
Meaning
Storage data check
Invalid storage address
Protect check.
Interface data check
If an error is indicated on cycle steal service
sequences that are not a part of IPL, the device retains
this information for presentation to the software via ISB
bits 4--7 at interruption time. Cycle steal operations are
terminated and an exception interrupt is presented. If an
error is indicated on IPL cycle steal sequences, the device
terminates cycle steal operations, but remains in an IPL
state with the IPL line active and does not present and end
interrupt. Therefore it is not necessary that status bus
bits be recorded during IPL for later presentation.
DPe
devices supporting IPL should especially note this.
2-12 GA34-0033
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