IBM Series 1 User Manual page 116

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the first device-end interrupt would range from 3 to 4 times
the selected time base. This is due to the asynchronous
nature of the internal free running oscillator or external
pulse train with respect to the program setting of the run
state or activation of the external gate. This uncertainty
must be taken into account only once each time a timer is
started.
There is also an uncertainty associated with the value
of the timers when measuring the duration of the external
gate in pulse duration applications. This is due to the
asynchronous nature of the external-gate deactivation with
respect to the internal clock or external pulse train. This
uncertainty is the time corresponding to plus or minus 1
count in the timer value after it is stopped.
Pulse averaging applications that use a known
fixed-time of external-gate activation and random pulses on
the customer clock input must also take into account a plus
or minus 1 count uncertainty in the timer value after it is
stopped
by the deactivation of the external gate.
When a machine check occurs, or when the Halt or Device
Reset commands are executed, the timers are stopped, the run
state is reset, the mode register is reset, and any pending
interrupt requests are reset. The prepare field, including
the I-bit, and the value in the timers are not reset.
When a system reset occurs, both timers are stopped,
the run state is reset, and the mode registers are reset.
The values held in the timers and auto-load registers are
not reset. The prepare field including the I-bit is reset.
When a power-on reset occurs, all resets caused
by
system reset occur; and in addition, the timers are reset to
their maximum value (that is, all ones), and the auto-load
registers are set to their maximum value.
Timer Feature 3-9