General Description; Customer Clock - IBM Series 1 User Manual

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General Description
The timer feature is addressed with the seven most
significant bits of the device address field in the IDCB.
The least significant bit (LSE) selects one of the two
timers within the attachment for all commands except
Prepare, where it is ignored. By convention, when the LSB
is 0, timer 0 is selected; when the LSB is 1, timer 1 is
selected. The seven most significant bits of the address
are changeable
by
jumper on the card; the
LSB
is not.
The timer feature is a DPC device and bas no cycle
steal or IPL capabilities.
The timer feature is connected to the processor I/O
channel through the following busses, as described in detail
in Chapter 2.
• Data bus--16 bits wide, bidirectional, with parity
checking and generating (odd parity per byte).
• Address bus--17 bits vide (00-16), receiving only; bit
16
is used to denote
a
DPC device command and to gate
receivers active.
• Request in bus--16 bits wide, driving only.
FUNCTIONAL DESCRIPTION OF THE EXTERNAL TIMER SIGNAL LINES
The timer has 4 external
signal
signal lines permit control
user-provided time base and gate.
the external signal lines; the
description of each signal.
lines per timer. These
of the timer with a
The following table lists
table is followed
by
a
Direction
Timer
X
customer clock -----------------) To Timer
Timer X external gate ------------------) To Timer
Timer X run state (-------------------- From Timer
Timer
X
external gate enable (---------
From
Timer
*All signals are down-level (minus) active.
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Active
level*
Down
Down
Down
Down
The timer X customer clock is the input for the
user-supplied clock or for a random pulse train. This input
uses the down level as active, not the down transition.
Timer Feature 3-5