IBM Series 1 User Manual page 212

c
c
c
yoes inactive, T5. This allo~s the processor to start
a new polling sequence for
d
request trom another
device if one is present.
9. After burst return is activated, the next activation of
service gate begins the burst transfer.
The
interface
throughput is now dedicated to the I/O devic€. The I/O
device continues to get service until burst
return
is
deactivated.
Burst return must
be
deactivated within
100
nanoseconds
of
the
activation
at
serv~ce gate for
the last transfer, T4. The I/O device must not present
another cycle steal request or an interrupt request
until service gate
return
goes inactive
for the
last
transfer, TS. This allows time for the processor to
start
a new
polliny
sequence and to
service
a
different
request if one is present.
10. In
both sequ~nces,
(1)
with poll return
and
(2) with
burst return, a channel timeout may occur. In the poll
sequence with poll return, the
timeout
occurs
if
poll
return does not go inactive. In the case of the poll
sequence with burst retur~, ~he timeout occurs
if
poll
does not go
inactive. Both
of these timeout
conditions
are indications of a tailure at the 1/0 device and will
not occur under norm~l operating conditions if the
timings in the referenced figures are adhered to. If
the channel timeout does occur, it causes a machine
check and activates the Halt or MCHK line on the
channel.
Processor I/O Channel
2-33