IBM Series 1 User Manual page 75

*1
*2
These lines are also driven by the 4953 processor in
conjunction
with
the storage interface.
(DR/BEC TYPE
C-C)
Neither processor uses these bits. They are therefore
tied up to the defined quiescent level at the
processor.
*3 Power-On-Reset is driven directly by the power supply
circuitry.
*4 The 4953 processor does not use Status Bus Bit 2 (for
storage protect). This line is therefore tied up to
the defined quiescent level.
*5 Address and Data Busses contain processor dependent
quiescent levels.
*6 The 4953 backpanel does not connect to
any
of these
pins.
*7 There is no connection to this pin for the first I/O
socket on the 4953 backpanel.
Figures 2-22 and 2-23 list further information on the
drivers and receivers for the 4953 and 4955 processors.
2-60 GA34-0033
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