IBM Series 1 User Manual page 60

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~ag2 ~nd ~ta Strobe. The previous section specified that
for DPC, interrupt service, and cycle steal service
sequences the deactivation of the return tag (address gate
return or service gate return) occurred only after the
deactivation of the respective outgoing tag (address gate or
service gat~ and data strobe.
Because the channel deactivates the outgoing tag
simultaneously with the deactivation of data strobe, the
phase relationships between the outgoing tag and data strobe
could be skewed at the device interface. At the device
interface, data strobe could be deactivated either before or
after the deactivation of the outgoing tag. However, data
strobe would never be active completely outside the active
envelope of the outgoing tag for that sequence. This
suggests that a method for keeping the return tag active to
meet the condition specified in the first paragraph is to
logically "OR" the outbound tag with the data strobe. This
is true, provided that certain considerations are taken into
account. First, as seen by any device, data strobe or
address gate can occur at random outside of a DPe sequence,
when address bus bit 16 is not active. This is because of
the presence of main storage physically attached to the
channel for the 4953 processor. Second, as seen by the poll
mechanism of any device, the data strobe can occur at
random. This is because of the concurrency of polling and
service sequences on the channel. A device adapter may
operate its poll mechanism while it or other devices are
executing a sequence associated with the service group.
These tvo considerations make it necessary to a) ensure that
the logical "ORfl is gated only for those sequences
specifically of interest to the attachment when it is
selected, and b) keep the poll mechanism operation
independent of data strobe.
Figure 2-16 illustrates a method for keeping the return
tags active for DPe, interrupt, and cycle steal sequences.
For a
ope
sequence, the logical "OR" of data strobe and
address gate is gated with the condition of a DPC selection
(address bus bit 16 active) and a match of the device
address with address bus bits 08--15. Por interrupt and
cycle steal service sequences, the selection is based upon
capturing the leading edge of the first service gate
following a poll capture.
The circuit shown enables the poll mechanism to be kept
independent of data strobe and prevents storage related data
strobes from activating the service gate return for a device
unless it has specifically been selected for service. Note
that address bus bit 16 is not used to determine selection
for the interrupt or cycle steal sequence. Note also that
data strobe does not participate in the setting of the
service gate capture trigger. The complement of the service
gate capture trigger resets the poll capture latch. This
ensures that the service gate capture trigger is fully
latched prior to resetting the poll capture latch, which in
turn removes the set condition for the service gate capture
trigger. The service gate capture trigger is reset by
either the deactivation of service gate or data strobe,
whichever occurs later in the sequence.
Processor I/O Channel 2-45