IBM Series 1 User Manual page 231

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The number of receiver.s that can be
connected to a bidirectional line is limited
by
the total
current that the receivers supply to the line relative to
the amount of current that a driver on the line can sink and
still maintain
a
down state within specification on the
line.
These limitations impose a major restriction to the
number of receivers that can be operated by a single driver.
Receiver conditioning relieves these limitations for
conventional technology
by
providing a means of gating off a
receiver when it is not the intended recipient of the
logic
signal on the bus. This allows a larger number of receivers
to be connected to the bus. Signals must be provided to
condition the receivers independent of the bus. It should
be understood, that conditioning in itself is not an
enabling or logical function; however, conditioning signals
are generated from logical conditions
in
the attachment.
Receiver conditioning is described
in
Figure 2-27.
When a receiver is fiot intended to be responsive to the
logic signal on the bus
(Va),
the control gate (conditioning
driver) holds the second input point of the receiver (Vb)
into the lower voltaqe or down state. Because the bus
driver contains a larger load than the conditioning driver,
the conditioning driver is able to sink more current than
the bus driver, thus making Va
>
Vb. It can be seen that,
when in this state, the current
Ib
is greater than Ia and
the receiver does not present a current load (as large as it
normally would) to the bus. Therefore, the receiver is said
to be conditioned off or inactive. Note that it is
important to choose a signal conditioning driver with a low
down level voltage in the region of 0.15 volts or less.
Selecting a
high current capability driver
and designing for
a low fan-out will also help to maintain this low down
level.
If the receiver is intended to be responsive to the
logic state on the bus, the control signal to the
conditioning driver releases the appropriate potential at Vb
to allow the receiver to be gated into a state responsive to
the logic signal at Va. The receiver is now said to be
conditioned on or active.
The address bus bits 8--15 receivers are conditioned
active only with address bus bit 16 being active. Address
bus bits 0--7 are conditioned active only during a
DPe
selection, which is in effect, address bus bit 16 being
active dnd a device address comparison. The data bus is
conditioned by two events: 1) during a DPC selection with
address hus bit 1 equal to a logical 1 and only until the
deactivation of addreSS gate return and, 2)
during a service
gate capture for a.
cycle steal service seqnence for an
output transfer and only until the a€activation of service
gate return.
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It is important that the receivers be conditioned
active only during the above mentioned events; they are to
be conditioned off or inactive all other times.
2-70
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