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Advantech MIC-3397 User Manual

Advantech MIC-3397 User Manual

6u compactpci 3rd generation intel quad-core xeon dual-core pentium processor blade with ecc support
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User Manual
MIC-3397
®
6U CompactPCI
3rd Generation
®
®
Intel
Quad-Core Xeon
&
®
Dual-Core Pentium
Processor
Blade with ECC support

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Summary of Contents for Advantech MIC-3397

  • Page 1 User Manual MIC-3397 ® 6U CompactPCI 3rd Generation ® ® Intel Quad-Core Xeon & ® Dual-Core Pentium Processor Blade with ECC support...
  • Page 2 No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable. How- ever, Advantech Co., Ltd.

  • Page 3: Declaration Of Conformity

    Class I, Division 2, Groups A, B, C and D indoor hazards. Technical Support and Assistance Visit the Advantech website at http://support.advantech.com where you can find the latest information about the product. Contact your distributor, sales representative, or Advantech's customer service center for technical support if you need additional assistance.

  • Page 4: Packing List

    If any item does not accord with the table, please contact your dealer immediately.  MIC-3397 all-in-one single board computer (CPU heatsink, PCH heatsink & MXM heatsink, and E6760 MXM Type A module optional included) x1  Daughter board for SATA HDD & SATA bracket (assembled) x 1 ...
  • Page 5 The sound pressure level at the operator's position according to IEC 704-1:1982 is no more than 70 dB (A). DISCLAIMER: This set of instructions is given according to IEC 704-1. Advantech disclaims all responsibility for the accuracy of any statements contained herein.
  • Page 6 Conformément à la norme CEI 704-1:1982, l'opérateur ne doit pas expérimenter un niveau sonore supérieur à 70 dB (A). AVERTISSEMENT: Ces consignes suivent la norme CEI 704-1. Advantech décline toute responsabilité concernant l'exactitude des déclarations con- tenues dans ce document. MIC-3397 User Manual...
  • Page 7 We Appreciate Your Input Please let us know of any aspect of this product, including the manual, which could use improvement or correction. We appreciate your valuable input in helping make our products better. MIC-3397 User Manual...
  • Page 8 MIC-3397 User Manual viii...

  • Page 9: Table Of Contents

    1.4.1 Clear CMOS (JP2)[m7] ............... 10 Connector Definitions................11 Table 1.8: MIC-3397 Connector Descriptions ......11 Figure 1.4 MIC-3397 8HP Front Panel Ports, Indicators and But- tons................11 Figure 1.5 MIC-3397 4HP Front Panel Ports, Indicators and But- tons................11 Figure 1.6 MIC-3397 4HP with On-board Features ....
  • Page 10 HDD................17 1.7.1 MIC-3397 HDD Installation Steps..........17 1.7.2 MIC-3397 Cfast Installation Steps ..........18 1.7.3 MIC-3397 Upgrade From 4HP to 8HP Installation Steps ... 19 Software Support ..................22 Chapter AMI BIOS Setup......... 23 Introduction ..................... 24 Figure 2.1 Setup program initial screen........24 BIOS Setup .....................
  • Page 11 Appendix C FPGA...........59 Features ....................60 FPGA I/O Registers ................60 Appendix D Glossary ..........61 Glossary ....................62 MIC-3397 User Manual...
  • Page 12 MIC-3397 User Manual...

  • Page 13: Chapter 1 Hardware Configuration

    Chapter Hardware Configuration This chapter describes how to configure MIC-3397 hardware.

  • Page 14: Introduction

    RTM), one PS/2 port, and one PCIe2.0 x4 interface reserved for user defined rear transition module. MIC-3397, is designed in single slot (4HP) and dual slot (8HP) form factor widths. The 8HP version provides rich and extensive I/O support, features high-performance discrete graphics using AMD Radeon E6760 GPU, supports 1 GB GDDR5 at PCIe x1, x2, x4, x8, and x16 lane widths, 2.5 GT/s and 5.0 GT/s link-data rates, up to four...

  • Page 15: Specifications

    CompactPCI Bus Interface The MIC-3397 is compliant with PICMG 2.0 Rev. 3.0. It supports a 64-bit / 33 MHz and 64-bit / 66 MHz PCI bus for up to 8 CompactPCI slots at 3.3 V or 5 V VIO. The MIC-3397 is hot-swap compliant (PICMG 2.1) and conforms to the CompactPCI...

  • Page 16: Bios

    1.2.5 Memory The MIC-3397 has up to 8 GB of onboard DDR3 memory and one 204-pin unbuf- fered DDR3 SO-DIMM sockets up to 8GB memory with ECC support. The following table shows a list of SO-DIMM modules that have been tested on the MIC-3397.

  • Page 17: Storage Interface

    1.2.7 Storage Interface The MIC-3397 supports four SATA II interfaces. The SATA1 interface can be routed to an on board 2.5" SATA hard disk drive or one 8G on board NAND flash by switch; the SATA 2 interface is routed to an on board Cfast module; SATA 3 & 4 are reserved to rear I/O via J3 connector for user customization.

  • Page 18: Optional Rear I/O Modules

    The RIO-3317 & RIO-3315 series are the optional RTM (also known as rear I/O mod- ule) for the MIC-3397.They offer a wide variety of I/O features, such as two or four RJ45 LAN ports, two COM ports, one VGA ports, two USB2.0 ports, one P/S2 port, or one Mini-SAS port on the certain model.

  • Page 19: Compactpci Mechanical Design

    6U/2 slot width (8HP): 1.35 kg (Bare board) 1.2.15 CompactPCI Mechanical Design MIC-3397 series is assembled with a copper heatsink for CPU & MXM, with alumi- num heatsink for PCH. However, forced air cooling in the chassis is still needed for operational stability and reliability.

  • Page 20: Xtm Connectors (Extension Module)

    1.2.18 XTM Connectors (Extension Module) MIC-3397 is extended by a XTM carrier board with one AMD E6760 MXM module via PCI Express gen2 x8 bus. 1.2.19 Hardware Monitor One Hardware Monitors (NCT6776D) is available to monitor critical hardware param- eters. It is to monitor CPU temperature and core voltage information.

  • Page 21: Table 1.6: Mic-3397 Jumper /Button & Switch Descriptions

    The MIC-3397 provides a system reset button on the front panel, it resets all payload and application-related circuitry. Table 1.6: MIC-3397 Jumper /Button & Switch Descriptions Number Function Clear CMOS System Reset Button Chandler Switch Table 1.7: MIC-3397 Switch Descriptions...

  • Page 22: Clear Cmos (Jp2)[M7]

    1.4.1 Clear CMOS (JP2)[m7] This jumper is used to erase CMOS data. MIC-3397 Clear CMOS will erase user password and system time information only, since we have implemented a CMOS backup mechanism. Likewise, if battery power is lost, CMOS forgets only system time and password.

  • Page 23: Connector Definitions

    Connector Definitions Tables 1.8 and 1.9 list the function of each connector of MIC-3397 and its RIO-3317, Figures 1.4 and 1.5 illustrate connector locations. Table 1.8: MIC-3397 Connector Descriptions Number Function J1/J2 Primary CompactPCI bus J3/J5 Rear I/O transition XTM1...

  • Page 24: Figure 1.7 Mic-3397 8Hp With Features

    MXM module E6760 MXM Heatsink Type A fom factor module MIC-3314 XTM carrier board Figure 1.7 MIC-3397 8HP with Features Figure 1.8 MIC-3314 XTM Carrier Board View Table 1.9: RIO-3317 Connector Descriptions Number Function RJ3/RJ5 Rear I/O transition RIO-3317-B1E USB2.0 pin header CN9/CN10 SATA2.0 on board connector...

  • Page 25: Usb Connectors

    1.5.1 USB Connectors The MIC-3397 provides up to six USB2.0 channels. Three USB ports are on the front panel. Three USBs are routed to rear I/O via the J5 connector–two on the RIO panel, the other via on-board connector. The USB interface provides complete plug and play, hot attach/detach for up to 127 external devices.

  • Page 26: Xtm Carrier Board (Mic-3314)

    1.5.7 Multi-Display Configuration There are a total of six display outputs from MIC-3397 dual slots SKU, with SM750 GPU on 4HP and E6760 MXM type A graphic module on the second layer. Two VGA from SM750, one DVI-D, one DVI-I and two DP from E6760.

  • Page 27: Figure 1.12Mic-3397 Five Multi-Display Configuration

    VGA output is provided, for a total of five simultaneous outputs. One main display + four extended displays based on resolution 1920x1080 (16 bit). Figure 1.12 MIC-3397 Five Multi-display configuration How to set up 1920x1080 resolution in resolution setting: Click "Advanced Setting"...

  • Page 28: Safety Precautions

    The MIC-3397 contains electro-statically sensitive devices. Please discharge your body and clothing before touching the assembly. Do not touch components or con- nector pins. We recommend that you perform assembly at an anti-static workbench. Figure 1.14 Complete Assembly of MIC-3397 Single Slot with SATA HDD MIC-3397 User Manual...

  • Page 29: Hdd

    Figure 1.15 Complete Assembly of MIC-3397 Dual Slot with SATA HDD 1.7.1 MIC-3397 HDD Installation Steps The MIC-3397 supports 2.5” SATA hard disk drive. The following steps illustrate the installation steps. Prepare SATA HDD and 4pcs M2.5 HDD screws. MIC-3397 User Manual...

  • Page 30: Mic-3397 Cfast Installation Steps

    HDD device into SATA daughter board connector. Fasten 4pcs HDD screws in holes to fix HDD device in place. 1.7.2 MIC-3397 Cfast Installation Steps The MIC-3397 supports Cfast. The following steps illustrate the installation steps. Prepare Cfast and 1pc M2.5 screw. MIC-3397 User Manual...

  • Page 31: Mic-3397 Upgrade From 4Hp To 8Hp Installation Steps

    Insert Cfast into Cfast socket, then fasten with screw as below. 1.7.3 MIC-3397 Upgrade From 4HP to 8HP Installation Steps The MIC-3397 supports 8HP configuration. The user can buy MIC-3314 assembly board (including XTM carrier board, MXM module, heatsink) to upgrade from 4HP to 8HP; follow installation steps below.
  • Page 32 Uninstall 4HP board as shown below. Prepare all 8HP required parts, including 4HP board, 8HP front panel, screw, post, MIC-3314 XTM assembly board. MIC-3397 User Manual...
  • Page 33 Fasten 5 screws, 5 posts and 6 VGA/DVI screws on XTM board top side, and install hot swap switch cable on 4HP board. Install 5 copper posts to assemble 4HP and XTM board. MIC-3397 User Manual...

  • Page 34: Software Support

    Software Support Windows 7, Windows Server 2008, Windows Server 2012, Fedora Linux 16, Red Hat Enterprise Linux 6.1 and Vxworks 6.9 have been tested on the MIC-3397. Please contact your local sales representative for details on support for other operating sys- tems.

  • Page 35: Ami Bios Setup

    Chapter AMI BIOS Setup This chapter describes how to configure the AMI BIOS.

  • Page 36: Introduction

    Setup information when the power is off. BIOS Setup The MIC-3397 Series system has AMI BIOS built in, with a CMOS SETUP utility that allows users to configure required settings or to activate certain system features. The CMOS SETUP saves the configuration in the CMOS RAM of the motherboard.

  • Page 37: Entering Setup

    Turn on the computer, and there should be a POST (Power-On Self Test) screen that shows the BIOS supporting the CPU, press <DEL> or <F2>, then you will immedi- ately be allowed to enter Setup. Figure 2.2 Press <DEL> or <F2> to Run Setup MIC-3397 User Manual...

  • Page 38: Main Setup

    System Date using the <Arrow> keys. Enter new values through the keyboard. Press the <Tab> key or the <Arrow> keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. MIC-3397 User Manual...

  • Page 39: Advanced Bios Features Setup

    2.3.2 Advanced BIOS Features Setup Select the Advanced tab from the MIC-3397 setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the <Arrow>...
  • Page 40 2.3.2.1 PCI Subsystem Setting  PCI Latency Timer Value to be programmed into PCI Latency Timer Register.  PCI Express Settings Set Maximum Payload of PCI Express Device or allow System BIOS to select the value. MIC-3397 User Manual...

  • Page 41: Figure 2.5 Trusted Computing

    2.3.2.2 Trusted Computing Figure 2.5 Trusted Computing  Security Device Support Disables BIOS support for security device. OS will not show Security Device. MIC-3397 User Manual...

  • Page 42: Figure 2.6 Cpu Configuration

    2.3.2.3 CPU Configuration Figure 2.6 CPU configuration  Hyper-Threading ® This item allows you to enable or disable Intel Hyper Threading technology. The default setting is “Enabled”. MIC-3397 User Manual...
  • Page 43 The default setting for this item is “Enabled”.  Adjacent Cache Line Prefetcher It allows users to enable or disable the adjacent cache lines prefetcher feature.  CPU Power Management Configuration It allows users to adjust CPU power related parameters. MIC-3397 User Manual...

  • Page 44: Figure 2.7 Sata Configuration

    Set to [AHCI mode] when you want the SATA hard disk drives to use the AHCI (Advanced Host Controller Interface). The AHCI allows the onboard storage driver to enable advanced serial ATA features that increase storage perfor- mance on random workloads by allowing the drive to internally optimize the order of commands. MIC-3397 User Manual...

  • Page 45: Figure 2.8 Usb Configuration

    This is a workaround item for any OS without EHCI hand-off support.  USB Mass Storage Devices Enable/Disable USB Mass Storage Support.  USB hardware delays and time-outs The recommended settings are as in the figure above. MIC-3397 User Manual...

  • Page 46: Figure 2.9 Cave Creek Siw Configuration

    Figure 2.9 Cave Creek SIW Configuration  Serial Port 0 Configuration Serial port 0 is from PCH chip Cave Creek. It allows users to set serial port 0 parameters by transfer mode from "RS232" to "RS422", default value is "RS232". MIC-3397 User Manual...

  • Page 47: Figure 2.10Super Io Configuration

    2.3.2.7 Super I/O Configuration Figure 2.10 Super IO Configuration  Serial Port 0/1 Configuration For serial port 0/1, IRQ/IO mode resource configuration, users can choose IRQ, IO and MODE. MIC-3397 User Manual...

  • Page 48: Figure 2.11H/W Monitor Configuration

    Transfer Mode It allows users to choose transfer mode as "RS232/422/485", default value is "RS232". 2.3.2.8 H/W Monitor Configuration System temperature, CPU temperature and voltage status can be checked in PC Health Status. Figure 2.11 H/W Monitor configuration MIC-3397 User Manual...

  • Page 49: Figure 2.12Serial Port Console Redirection Configuration

    2.3.2.9 Serial Port Console Redirection Figure 2.12 Serial Port Console Redirection configuration  Console Redirection This item allows users to enable or disable console redirection or Microsoft Win- dows Emergency Management Services (EMS). MIC-3397 User Manual...

  • Page 50: Figure 2.13Network Stack Configuration

    2.3.2.10 Network Stack Figure 2.13 Network Stack configuration  Network Stack This option allows you to enable or disable the Network Stack function. The default setting is “Disabled”. MIC-3397 User Manual...

  • Page 51: Chipset Configuration Setting

    Users can display a Chipset Setup option by highlighting it using the <Arrow> keys. All Chipset Setup options are described in this section. The Chipset Setup screens are shown below. The sub menus are described on the following pages. 2.3.3.1 South Bridge MIC-3397 User Manual...

  • Page 52: Figure 2.14Chipset Configuration

    4HP only while 8HP means default is from E6760 MXM graphics module.  Lan5 Selector Lan 5 interface is switchable for front and rear, it allows users to choose LAN 5 output from 4HP front panel or from RTM. MIC-3397 User Manual...

  • Page 53: Boot Setting

    This item allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.  Boot Mode Select This item allows users to select boot mode as "Legacy or UEFI".  Fixed Boot Order Priorities The option shows device boot priorities. MIC-3397 User Manual...
  • Page 54 This option allows you to set the display mode for Option ROM with "Force BIOS" or "Keep Current". The default setting is "Force BIOS". – INT19 Trap Response This option allows you to choose "Immediate" execute the trap right away or choose "Postponed" to execute the trap during legacy boot. MIC-3397 User Manual...
  • Page 55 Other PCI device ROM priority It is for devices other than Network, Mass storage or Video; it defines which OpROM to launch  Hard Drive BBS Priorities This option specifies the boot device priority sequence from available hard disk drives. MIC-3397 User Manual...

  • Page 56: Security Setup

    Select this option and press <ENTER> to access the sub menu, and then type in the password. Set the Administrator password.  User Password Select this option and press <ENTER> to access the sub menu, and then type in the password. Set the User Password. MIC-3397 User Manual...
  • Page 57  HDD Security Configuration – Set User Password Select this option and press <ENTER> to access the sub menu, and then type in the password. Set the HDD User Password. MIC-3397 User Manual...

  • Page 58: Save & Exit Option

    Save Configuration and Reset? [Yes] [No] Select Yes or No.  Discard Changes and Reset Select “Discard Changes and Reset” and press <Enter>. The following mes- sage appears: Reset without saving? [Yes] [No] Select Yes to discard changes and reset. MIC-3397 User Manual...
  • Page 59 Defaults are designed for maximum system perfor- mance, but may not work best for all computer applications. In particular, do not use the Defaults if the computer is experiencing system configuration problems. Select Restore Defaults from the Exit menu and press <Enter>. MIC-3397 User Manual...
  • Page 60 MIC-3397 User Manual...

  • Page 61: Appendix A Pin Assignments

    Appendix Pin Assignments This appendix describes pin assignments.

  • Page 62: J1 Connector

    B22 GND 3.3V D22 PAD6 PAD5 F22 GND 3.3V B23 PAD4 PAD3 D23 5V PAD2 F23 GND PAD1 B24 5V V(I/O) D24 PAD0 ACK64# F24 GND B25 RQ64# ENUM# D25 3.3V F25 GND Note! NC = no connection MIC-3397 User Manual...

  • Page 63: J2 Connector

    C19 IPMB_PWR D19 IPMB_PWR E19 A20 J1_CLK5 B20 NC C20 NC D20 GND E20 NC A21 J1_CLK6 B21 GND C21 NC D21 NC E21 NC A22 GA4 B22 GA3 C22 GA2 D22 GA1 E22 GA0 Note! NC = no connection MIC-3397 User Manual...

  • Page 64: J3 Connectors

    J3_MDIB0 J3_MDIB2 B16 J3_MDIB0- C16 GND E16 J3_MDIB2- J3_MDIA1 J3_MDIA3 B17 J3_MDIA1- C17 GND E17 J3_MDIA3- J3_MDIA0 J3_MDIA2 B18 J3_MDIA0- C18 GND E18 J3_MDIA2- RIO_SATA B19 NC D19 NC E19 NC _LED# Note! NC = no connection MIC-3397 User Manual...

  • Page 65: J5 Connector

    LAN4_LIN RIO_COM RIO_COM2 _RX# _CTS# K-ACT# 2_DCD# _TX# RIO_COM1 RIO_COM1 RTM_PRE RIO_COM RIO_COM2 _TX1 _DSR# 2_RTS# _DTR# RIO_COM1 RIO_COM1 RIO_COM RIO_COM2 C21 NC _RTS# _DTR# 2_CTS# __RI# RIO_COM1 RIO_COM1 RIO_COM RIO_COM2 C22 NC _DCD# _RI# 2_DSR# _RX# MIC-3397 User Manual...

  • Page 66: Other Connectors

    PE_XTM_SW_RXN6 PE_XTM_SW_RXN7 PCH_WAKE# XTM_PLTRST# XTM_GPIO1 XTM_GPIO2 MXM_TH_OVERT# 3VSBPWM_EN XTM_PWREN 3VSB_EN +3V3 MXM_PWROK +3V3 MXM_PWR_EN +3V3 +3V3 PE_XTM_SW_TXP0 PE_XTM_SW_TXP1 PE_XTM_SW_TXN0 PE_XTM_SW_TXN1 PE_XTM_SW_TXP2 PE_XTM_SW_TXP3 PE_XTM_SW_TXN2 PE_XTM_SW_TXN3 PE_XTM_SW_TXP4 PE_XTM_SW_TXP5 PE_XTM_SW_TXN4 PE_XTM_SW_TXN5 PE_XTM_SW_TXP6 PE_XTM_SW_TXP7 PE_XTM_SW_TXN6 PE_XTM_SW_TXN7 CLK_100M_XTM_PEG_DP SMBDAT1 CLK_100M_XTM_PEG_DN SMBCLK1 XTM_PRESENT# MIC-3397 User Manual...

  • Page 67: Table A.6: Spi1/Spi2 Connector

    Table A.6: SPI1/SPI2 Connector SPI_R_CS#0 SPI_R_CS#1 SPI_SO0 SPI_SO1 FWH1_WP# FWH2_WP# SPI_SI0 SPI_SI1 SPI_S_CK0 SPI_S_CK1 SPI_HD0 SPI_HD1 +3V3_SB +3V3_SB MIC-3397 User Manual...
  • Page 68 MIC-3397 User Manual...

  • Page 69: Appendix B Programming The Watchdog Timer

    Appendix Programming the Watchdog Timer This appendix describes how to program the watchdog timer.

  • Page 70: Watchdog Timer Programming Procedure

    After data entry, your program must refresh the watchdog timer by rewriting the I/O port 443 and 443 (hex) while simultaneously setting it. When you want to disable the watchdog timer, your program should read I/O port 444 (hex). MIC-3397 User Manual...

  • Page 71: Fpga

    Appendix FPGA This appendix describes FPGA configuration.

  • Page 72: Features

    Debug Message: Boot time POST message FPGA I/O Registers The Advantech MIC-3397 FPGA communicates with main I/O spaces. The LPC unit is used to interconnect the Intel LPC signals. The Debug Port Unit is used to decode POST codes. The Watchdog is used to detect BIOS ready signal or recover BIOS code from redundant BIOS flash.
  • Page 73 Appendix Glossary...

  • Page 74: Appendix D Glossary

    An Interface specified by Electronic Industries Alliance Real Time Clock Rear Transition Module Single Board Computer SDRAM Synchronous DRAM Small Form-factor Pluggable Serial Presence Detect Serial Peripheral Interface Solid State Disk SoftWare Ultra Low Voltage PCIe Interface Mezzanine Card Extension Module MIC-3397 User Manual...
  • Page 75 MIC-3397 User Manual...
  • Page 76 No part of this publication may be reproduced in any form or by any means, electronic, photocopying, recording or otherwise, without prior written permis- sion of the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd. 2016...

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