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Advantech MIO-5373 User Manual

Advantech MIO-5373 User Manual

3.5" mi/o-compact sbc, 8th gen. intel core u-series i7/i5/i3/celeron, ddr4, emmc, hdmi, dp, 48-bit lvds, 2 gbe, m.2 b key 2280, dc-in 12-24v, imanager
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User Manual
MIO-5373
MIO-5373 3.5" MI/O-Compact SBC,
8th Gen. Intel® Core™ U-series (i7/
i5/i3/Celeron®), DDR4, eMMC, HDMI,
DP, 48-bit LVDS, 2 GbE, M.2 B key
2280, DC-in 12-24V, iManager

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Summary of Contents for Advantech MIO-5373

  • Page 1 User Manual MIO-5373 MIO-5373 3.5" MI/O-Compact SBC, 8th Gen. Intel® Core™ U-series (i7/ i5/i3/Celeron®), DDR4, eMMC, HDMI, DP, 48-bit LVDS, 2 GbE, M.2 B key 2280, DC-in 12-24V, iManager...
  • Page 2 No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. The information provided in this manual is intended to be accurate and reliable.
  • Page 3 Because of Advantech’s high quality-control standards and rigorous testing, most of our customers never need to use our repair service. If an Advantech product is defec- tive, it will be repaired or replaced at no charge during the warranty period. For out- of-warranty repairs, you will be billed according to the cost of replacement materials, service time and freight.
  • Page 4 Discard used batteries according to the manufacturer's instruc- tions. Technical Support and Assistance Visit the Advantech website at http://support.advantech.com to obtain the latest product information. Contact your distributor, sales representative, or Advantech's customer service center for technical support if you need additional assistance. Please have the following information ready before you call: –...
  • Page 5 (P/N: 1700019584)  1 x COM RS-232 Cable 20cm (P/N: 1700030404-01)  1 x MIO-5373 Heatsink for 0 ~ 60°C (P/N: 1960091427N001)  1 x Mini Jumper (P/N: 9689000002) If any of these items are missing or damaged, contact your distributor or sales repre- sentative immediately.
  • Page 6 MIO-5373 User Manual...

  • Page 7: Table Of Contents

    Environmental ................5 Block Diagram................... 6 Board Dimensions..................6 Figure 1.1 MIO-5373 Mechanical Drawing (Top Side) ....6 Figure 1.2 MIO-5373 Mechanical Drawing (Bottom Side) ... 7 Figure 1.3 MIO-5373 Mechanical Drawing (Coastline)....7 Figure 1.4 MIO-5373 Mechanical Drawing (with Heatsink) ..7 Chapter Installation..........9...
  • Page 8 First MB Memory Map................96 Table B.3: First MB Memory Map ..........96 Interrupt Assignments ................97 Table B.4: Interrupt Assignments ..........97 Appendix C Watchdog Timer Sample Code ..99 Watchdog Timer Sample Code............. 100 MIO-5373 User Manual viii...

  • Page 9: Chapter 1 General Information

    Chapter General Information This chapter gives background information regarding MIO-5373.  Introduction  Specifications  Block Diagram  Board Layout and Dimensions...

  • Page 10: Introduction

    Introduction MIO-5373, 3.5 SBC w/ MIOe, powered by 8th Gen. Intel® Core i7/i5/i3/Celeron pro- cessors, which has low power features, high performance computing, and multimedia capabilities. To meet numerous demands from embedded product applications, MIO- 5373 developed an optimized thermal solution; it makes the possibility of fanless design on this type of high performance platform.
  • Page 11 Multiple Display: Triple simultaneous displays by 48-bit LVDS/ eDP+HDMI+DP – LCD: LVDS Dual Channel 48-bit up to 1920 x 1200 Option eDP1.4 up to 4096x2304@60Hz – HDMI/DP: 1 Port HDMI1.4 up to 4096x2160@30/24Hz 1 Port DP1.2 up to 4096x2306@60Hz MIO-5373 User Manual...

  • Page 12: Os Support

     – TPM2.0, only support under UEFI mode 1.2.2 OS Support MIO-5373 supports Win10 64-bit (UEFI mode only) For further information about OS support of MIO-5373, please Advantech website or contact the technical support center. http://support.advantech.com.tw/ 1.2.3 Mechanical Specifications ...

  • Page 13: Electrical Specifications

    Operating: 40°C @ 95% relative humidity, non-condensing – Storage: 60°C @ 95%relative humidity, non-condensing Vibration Resistance: 3.5Grms  Not supported by default. Please contact Advantech if this function is needed. Thermal conditions need to be considered when setting maximum frequency. MIO-5373 User Manual...

  • Page 14: Block Diagram

    (w/ CNL-LP) M.2 B-key 2280 Audio USB2.0 M.2 B-key 3042 LAN1 (i219) i219 MIOe LAN2 (i210) i210 USB3.1 P0~P3 COM2 RS-232/422/485 eMMC5.1 CANBus COM1 RS-232/422/485 TPM2.0 EIO-201 GPIO16b SMBus Board Dimensions Figure 1.1 MIO-5373 Mechanical Drawing (Top Side) MIO-5373 User Manual...
  • Page 15 Figure 1.2 MIO-5373 Mechanical Drawing (Bottom Side) Figure 1.3 MIO-5373 Mechanical Drawing (Coastline) Figure 1.4 MIO-5373 Mechanical Drawing (with Heatsink) MIO-5373 User Manual...
  • Page 16 MIO-5373 User Manual...

  • Page 17: Chapter 2 Installation

    Chapter Installation This chapter explains the setup procedures of the MIO-5373 hard- ware, including instructions on setting jumpers and connecting peripherals, switches and indica- tors. Be sure to read all safety pre- cautions before you begin the installation procedure.

  • Page 18: Jumpers & Switches

    Jumpers & Switches MIO-5373 has a number of jumpers that allow you to configure your system to suit your application. The table below lists the functions of the various jumpers. Table 2.1: Jumpers & Switches AT/ATX mode selection RI# 5V/12V selection pin for CN9...

  • Page 19: Connector Locations

    Connector Locations Figure 2.1 MIO-5373 Connector Locations (Top Side) CN14 CN16 CN17 CN30A1 CN20 Figure 2.2 MIO-5373 Connector Locations (Bottom Side) Figure 2.3 MIO-5373 Connector Locations (Coastline) MIO-5373 User Manual...

  • Page 20: Setting Jumpers

    Generally, you simply need a standard cable to make most connections. Jumper Settings 2.5.1 J1: ATX/AT Mode Selection Function Jumper Setting AT Mode (Default) ATX Mode Signal Pin Definition AT_DET# MIO-5373 User Manual...

  • Page 21: J2: Ri# 5V/12V Selection Pin For Cn9

    2.5.2 J2: RI# 5V/12V selection pin for CN9 Function Jumper Setting RI# Voltage Setting: +V5 RI# Voltage Setting: +V12 RI# Voltage Setting: RI# (Default) Signal Pin Definition CN9_RI# COM_RI# CN9_RI# +V12 CN9_RI# MIO-5373 User Manual...

  • Page 22: J3: Panel Voltage Selection

    Panel Voltage Setting: +V3.3(Default) Panel Voltage Setting: +V5 Panel Voltage Setting: +V12 Signal Pin Definition +V3.3 +V_CH7511B_LCD +V12 2.5.4 J4: JEIDA and VESA mode Selection Function Jumper Setting JEIDA mode Setting: +V3.3 VESA mode Setting: GND (Default) MIO-5373 User Manual...

  • Page 23: Sw1: Clear Cmos

    Signal Pin Definition LVDS1_VCON LVDS1_VCC 2.5.5 SW1: Clear CMOS Function Jumper Setting Keep COMS Data (Default) Clear CMOS Date Signal Pin Definition RTC_a_RST# RTC_RST# MIO-5373 User Manual...
  • Page 24 MIO-5373 User Manual...

  • Page 25: Chapter 3 Ami Bios Setup

    Chapter AMI BIOS Setup...
  • Page 26 AMIBIOS has been integrated into a plethora of motherboards for decades. With the AMIBIOS Setup program, you can modify BIOS settings and control the various sys- tem features. This chapter describes the basic navigation of the MIO-5373 BIOS setup screens.

  • Page 27: Entering Setup

    BIOS supports your CPU. If there is no number assigned to the patch code, please contact an Advantech application engineer to obtain an up-to-date patch code file. This will ensure that your CPU's system status is valid.

  • Page 28: Advanced Bios Features Setup

    3.1.2 Advanced BIOS Features Setup Select the Advanced tab from the MIO-5373 setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the <Arrow>...
  • Page 29  MonitorMWait Enable/Disable MonitorMWait.  Intel Trusted Execution Technology Enables utilization of additional hardware capability provided by Intel® Trusted Execution Technology. 3.1.2.2 Power & Performance  CPU - Power Management Control CPU - Power Management Control Options. MIO-5373 User Manual...
  • Page 30 Enable/Disable Platform Power Limit 1 programming.  Power Limit 4 Override Enable/Disable Power Limit 4 override.  C states Enable/Disable CPU Power Management.  PowerLimit 3 Settings Power Limit 3 Settings.  CPU Lock Configuration CPU Lock Configuration. MIO-5373 User Manual...
  • Page 31 Package Power Limit MSR Lock  Enable/Disable locking of Package Power Limit settings.  Energy Efficient Turbo Enable/Disable Energy Efficient Turbo feature. Config TDP Configurations  Configurable TDP Boot Mode Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. MIO-5373 User Manual...
  • Page 32 CTDP BIOS control Enables CTDP control via runtime ACPI BIOS method. Power Limit 3 Settings  Power Limit 3 Override Enable/Disable Power Limit 3 override. CPU Lock Configuration  CFG Lock Configure MSR 0xE2[15], CFG Lock bit. MIO-5373 User Manual...
  • Page 33 Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR. GT - Power Management Control  RC6(Render Standby) Check to enable render standby support.  Maximum GT frequency Maximum GT frequency limited by user. Disable Turbo GT frequency  Enabled/Disabled Turbo GT frequency. 3.1.2.3 PCH-FW Configuration MIO-5373 User Manual...
  • Page 34 Select the highest ACPI sleep state the system will enter when the SUSPEND- button is pressed.  Lock Legacy Resources Enables or Disables Lock of Legacy Resources.  S3 Video Repost Enable or Disable S3 Video Repost. MIO-5373 User Manual...
  • Page 35 Enable/Disable Wake on Ring Function.  Hardware Monitor Monitor hardware Status.  Watch Dog Timer Configuration Watch Dog Timer Configuration Page.  Case Open Detection Enable or Disable Case Open Detect Function.  GPIO Configuration GPIO Configuration Settings. MIO-5373 User Manual...
  • Page 36 Enable or Disable Serial Port (COM). Change Settings  Select an optimal settings for Super IO device.  COM Port Mode COM Port Mode Select. Serial Port 2 Configuration  Serial Port Enable or Disable Serial Port (COM). MIO-5373 User Manual...
  • Page 37  Change Settings Select an optimal settings for Super IO device.  COM Port Mode COM Port Mode Select. Hardware Monitor Watch Dog Timer Configuration  Watch Dog Timer Enable or Disable Watch Dog Timer Function. MIO-5373 User Manual...
  • Page 38 Configure GPIO0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15. 3.1.2.6 Trusted Computing  Security Device Support Enable or disable BIOS support for security device.  SHA-1 PCR Bank Enable or Disable SHA-1 PCR Bank.  SHA256 PCR Bank Enable or Disable SHA256 PCR Bank. MIO-5373 User Manual...
  • Page 39 TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices. 3.1.2.7 S5 RTC Wake Settings  Wake system from S5 Enable or disable System wake on alarm event. Select FixedTime, system will- wake on the hr::min::sec specified. MIO-5373 User Manual...
  • Page 40 This item allows users to enable or disable console redirection for Microsoft Windows Emergency Management Services (EMS).  Console Redirection This item allows users to configuration console redirection detail settings. 3.1.2.9 Intel TXT Information  Intel TXT Information Display Intel TXT information. MIO-5373 User Manual...
  • Page 41 Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor. MIO-5373 User Manual...
  • Page 42 Storage Controls the execution of UEFI and Legacy Storage OpROM. Video  Controls the execution of UEFI and Legacy Video OpROM.  Other PCI devices Determines OpROM execution policy for devices other than Network, Storage, or Video. MIO-5373 User Manual...
  • Page 43 3.1.2.12 NVMe Configuration 3.1.2.13 SDIO Configuration  SDIO Access Mode Select access SD device in DMA mode or PIO mode. MIO-5373 User Manual...

  • Page 44: Chipset Configuration

    3.1.3 Chipset Configuration Select the Chipset tab from the MIO-5373 setup screen to enter the Chipset BIOS Setup screen. You can display a Chipset BIOS Setup option by highlighting it using the <Arrow> keys. All Plug and Play BIOS Setup options are described in this sec- tion.
  • Page 45 Memory Configuration Parameters.  Graphics Configuration Graphics Configuration Parameters.  VT-d VT-D capability.  Above 4GB MMIO BIOS assignment Enable/Disable above 4GB Memory Mapped IO BIOS assignment.  X2APIC Opt Out Enable/Disable X2APIC Opt Out Bit. Memory Configuration MIO-5373 User Manual...
  • Page 46  Gfx Low Power Mode This option is applicable for SFF only.  PM Support Enable/Disable PM Spport.  PAVP Enable Enable/Disable PAVP.  CD Clock Frequency Select the highest Cd clock frequency supported by this platform. MIO-5373 User Manual...
  • Page 47 Color depth and data packing format for Non-EDID Support.  Dual LVDS mode Select LVDS bus to Single bus mode or Dual bus mode.  LVDS Panel Type This item allow user to select LVDS panel type. 3.1.3.2 PCH-IO Configuration MIO-5373 User Manual...
  • Page 48 Enable or Disable onboard LAN's PXE option ROM. PCIE Wake  Enable or Disable PCIE to wake the system from S5.  State After S3 Specify what state to go to when power is re-applied after a power failure (G3 state). PCI Express Configuration MIO-5373 User Manual...
  • Page 49 Indicates the maximum speed the SATA controller can support.  Software Feature Mask Configuration RST Legacy ROM/RST UEFI Driver will refer to the SWFM configuration to enable/disable the storage feature.  Aggressive LPM Support Enabled PCH to aggressively enter link power state. MIO-5373 User Manual...
  • Page 50 Selectively Enable/Disable the corresponding USB Port from reporting a Device Connection to the Controller. Security Configuration  RTC Lock Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM.  BIOS Lock Enable or Disable the PCH BIOS Lock Enable feature. MIO-5373 User Manual...
  • Page 51 HD Audio Configuration  HD Audio Control Detection of the HD-Audio device. Disabled = HDA will be uncondition- ally disabled. Enabled = HDA will be unconditionally Enabled. SerialIO Configuration  I2C0 Controller Enable/Disables SerialIO Controller. MIO-5373 User Manual...
  • Page 52 SCS Configuration  eMMC 5.0 Controller Enable or Disable SCS eMMC 5.0 Controller. MIO-5373 User Manual...

  • Page 53: Security

    3.1.4 Security Select Security Setup from the MIO-5373 Setup main BIOS setup menu. All Security Setup options, such as password protection and virus protection are described in this section. To access the sub menu for the following items, select the item and press <Enter>:...

  • Page 54: Boot

     Boot Option #1 Sets the system boot order.  Fast Boot Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options. MIO-5373 User Manual...

  • Page 55: Save & Exit

    This item allows you to save the changes done so far as user defaults.  Restore User Defaults This item allows you to restore the user defaults to all the options.  Boot Override Boot device select can override your boot priority. MIO-5373 User Manual...
  • Page 56 MIO-5373 User Manual...

  • Page 57: Chapter 4 Mioe Installation

    Chapter MIOe Installation...

  • Page 58: Quick Installation Guide

    There is a heatsink/cooler in the white box inside the package. Carefully remove the release paper from the thermal pad before installation. Remove release paper There are eight screws, six studs, and two nuts inside the white box, please install the heatsink into place and follow assembly sequence below: MIO-5373 User Manual...
  • Page 59 MIO-5373 User Manual...
  • Page 60 MIO-5373 User Manual...

  • Page 61: Appendix A Pin Assignments

    Appendix Pin Assignments This appendix contains informa- tion of a detailed or specialized nature.

  • Page 62: Jumper Settings

    J1: ATX/AT Mode Selection Function Jumper Setting AT Mode (Default) ATX Mode Signal Pin Definition AT_DET# A.1.2 J2: RI# 5V/12V selection pin for CN9 Function Jumper Setting RI# Voltage Setting: +V5 RI# Voltage Setting: +V12 RI# Voltage Setting: RI# (Default) MIO-5373 User Manual...

  • Page 63: J3: Panel Voltage Selection

    Signal Pin Definition CN9_RI# COM_RI# CN9_RI# +V12 CN9_RI# A.1.3 J3: Panel Voltage Selection Function Jumper Setting Panel Voltage Setting: +V3.3(Default) Panel Voltage Setting: +V5 Panel Voltage Setting: +V12 Signal Pin Definition +V3.3 +V_CH7511B_LCD +V12 MIO-5373 User Manual...

  • Page 64: J4: Jeida And Vesa Mode Selection

    J4: JEIDA and VESA mode Selection Function Jumper Setting JEIDA mode Setting: +V3.3 VESA mode Setting: GND (Default) Signal Pin Definition LVDS1_VCON LVDS1_VCC A.1.5 SW1: Clear CMOS Function Jumper Setting Keep COMS Data (Default) Clear CMOS Date Signal Pin Definition RTC_a_RST# RTC_RST# MIO-5373 User Manual...

  • Page 65: Connector And Header List

    HDD Connector CN26 HDD Connector CN27 GPIO/RS232 Connector CN28 Audio Connector CN29 GPIO/RS232 Connector CN30 MIOe Connector CN30A1 I2C Bus Connector CN31 System FAN Connector CN32 CANBus Connector CN35 SMBus Connector CN36 DC input Connector (Adapter) CN37 MIO-5373 User Manual...

  • Page 66: Connector And Header List Description

    Connector and Header List Description A.3.1 DC input Connector Signal Pin Definition +V24_V12_DC_IN +V24_V12_DC_IN A.3.2 DC input Connector (Adapter) Signal Pin Definition +V24_V12_DC_IN MIO-5373 User Manual...

  • Page 67: Rj45 (2 Port)

    A.3.3 RJ45 (2 port) Signal Pin Definition LAN1_MDIO+ LAN1_MDIO- LAN1_MDI1+ LAN1_MDI1- LAN1CONN LAN1_GND LAN1_MDI2+ LAN1_MDI2- LAN1 MDI3+ MIO-5373 User Manual...

  • Page 68: I2C Bus Connector

    LAN1_MDI3- LAN1_ACT# LAN1_A_ACT# LAN1_A_LINK100# LAN1_A_LINK1000# LAN2_MDIO+ LAN2_MDIO- LAN2_MDI1+ LAN2_MDI1- LAN2CONN LAN2_GND LAN2_MDI2+ LAN2_MDI2- LAN2_MDI3+ LAN2_MDI3- LAN2_ACT# LAN2_A_ACT# LAN2_A_LINK100# LAN2_A_LINK1000# A.3.4 I2C Bus Connector Signal Pin Definition I2C_DAT I2C_CLK MIO-5373 User Manual...

  • Page 69: Smbus Connector

    A.3.5 SMBus Connector Signal Pin Definition SMBus_DAT SMBus_CLK A.3.6 System FAN Connector Signal Pin Definition +12V FAN_SPEED FAN_PWM MIO-5373 User Manual...

  • Page 70: Internal Usb Connector

    A.3.7 Internal USB Connector Signal Pin Definition +V5SB +V5SB USB8_P- USB9_P- USB8_P+ USB9_P+ A.3.8 HDMI and DP++ Connector Signal Pin Definition Signal Pin Definition HDMI1_Z_TX2+ DP_TX0+ HDMI1_Z_TX2- DP_TX0- HDMI1_Z_TX1+ DP_TX1+ HDMI1_Z_TX1- DP_TX1- HDMI1_Z_TX0+ DP_TX2+ HDMI1_Z_TX0- DP_TX2- MIO-5373 User Manual...

  • Page 71: Com Port Connector (Rs232+Rs422+Rs485)

    HDMI1_Z_DCLK+ DP_TX3+ HDMI1_Z_DCLK- DP_TX3- DP_AUX_EN# HDMI1_SCL DP_AUX+ HDMI1_SDA DP1_AUX- +V5_HDMI1 DDP2_DP_HPD DDP1_HDMI_HPD +V3.3_DP A.3.9 COM port Connector (RS232+RS422+RS485) Signal Pin Definition 422TX-/485D-/DCD# 422TX+/485D+/RXD 422RX+/TXD 422RX-/DTR# DSR# RTS# CTS# A.3.10USB3.1 Connector (2 ports) MIO-5373 User Manual...

  • Page 72: Usb3.1 Connector (2 Ports)

    Signal Pin Definition USB1_P- USB1_P+ USB1_SSRX- USB1_SSRX+ USB1_SSTX- USB1_SSTX+ USB2_P- USB2_P+ USB2_SSRX- USB2_SSRX+ USB2_SSTX- USB2_SSTX+ A.3.11 USB3.1 Connector (2 ports) Signal Pin Definition USB3_P- USB3_P+ USB3_SSRX- USB3_SSRX+ USB3_SSTX- MIO-5373 User Manual...

  • Page 73: Ddr4 Sodimm 260P/H9.2Mm

    USB3_SSTX+ USB4_P- USB4_P+ USB4_SSRX- USB4_SSRX+ USB4_SSTX- USB4_SSTX+ A.3.12DDR4 SODIMM 260P/H9.2mm Signal Pin Definition MB_MD8 MB_MD11 MB_MD15 MB_MD14 MB_DQS1- +V1.2DDR MB_DQS1+ MB_MD12 MB_MD13 MIO-5373 User Manual...
  • Page 74 MB_MD9 MB_MD10 MB_MD2 MB MD3 MB_MD7 MB_MD0 MB_DQS0- +V1.2DDR MB_DQS0+ MB_MD1 MB_MD4 MB_MD6 MB_MD5 MB_MD21 MB_MD17 MB_MD20 MB_MD16 MB_DQS2- +V1.2DDR MB_DQS2+ MB_MD23 MB_MD18 MB_MD22 MB_MD19 MB_MD28 MB_MD29 MIO-5373 User Manual...
  • Page 75 MB_MD25 MB_MD24 MB_DQS3- +V1.2DDR MB_DQS3+ MB_MD30 MB_MD26 MB_MD31 MB_MD27 MB_CB5 MB_CB4 MB_CB1 MB_CB0 MB_DQS8- +V1.2DDR MB_DQS8+ MB_CB6 MB_CB2 MB_CB7 MB_CB3 DDR4_DRAMRST# MB_CKE0 MB_CKE1 +V1.2DDR +V1.2DDR MB_BG1 MB_ACT# MB_BG0 MIO-5373 User Manual...
  • Page 76 MB_MA5 MB_MA6 MB_MA4 +V1.2DDR +V1.2DDR MB_MA3 MB_MA2 MB_MA1 DDR1_B_EVENT# +V1.2DDR +V1.2DDR MB_CLK_DDRB0+ MB_CLK_DDRB1+ MB_CLK_DDRB0- MB_CLK_DDRB1- +V1.2DDR +V1.2DDR DDR1_B_PARITY MB_MA0 MB_BA1 MB_MA10 +V1.2DDR +V1.2DDR MB_SCS#0 MB_BA0 MB_SWE# MB_SRAS# +V1.2DDR +V1.2DDR MB_ODT0 MB_SCAS# MB_SCS#1 MB_MA13 +V1.2DDR +V1.2DDR MB_ODT1 +V1.2DDR MIO-5373 User Manual...
  • Page 77 DDR1_VREF_Z_DQ DIMMB_SA2 MB_MD38 MB_MD34 MB_MD35 MB_MD39 MB_DQS4- +V1.2DDR MB_DQS4+ MB_MD36 MB_MD33 MB_MD37 MB_MD32 MB_MD44 MB_MD40 MB_MD45 MB_MD41 MB_DQS5- +V1.2DDR MB_DQS5+ MB_MD42 MB_MD47 MB_MD46 MB_MD43 MB_MD52 MIO-5373 User Manual...
  • Page 78 MB_MD49 MB_MD48 MB_MD53 MB_DQS6- +V1.2DDR MB_DQS6+ MB_MD55 MB_MD50 MB_MD54 MB_MD51 MB_MD60 MB_MD57 MB_MD56 MB_MD61 MB_DQS7- +V1.2DDR MB_DQS7+ MB_MD62 MB_MD63 MB_MD59 MB_MD58 SMB_CLK SMB_DAT +V3.3 DIMMB_SAO +V2.5_VPP +V0.6 VTT +V2.5_VPP MIO-5373 User Manual...

  • Page 79: Ddr4 Sodimm 260P/H9.2Mm

    DIMMB_SA1 A.3.13DDR4 SODIMM 260P/H9.2mm Signal Pin Definition MA_MD4 MA_MD1 MA_MDO MA_MD5 MA_DQSO- +V1.2DDR MA_DQSO+ MA_MD6 MA_MD7 MA_MD2 MA_MD3 MA_MD9 MA_MD13 MIO-5373 User Manual...
  • Page 80 MA_MD8 MA_MD12 MA_DQS1- +V1.2DDR MA_DQS1+ MA_MD15 MA_MD10 MA_MD14 MA_MD11 MA_MD21 MA_MD16 MA_MD20 MA_MD17 MA_DQS2- +V1.2DDR MA_DQS2+ MA_MD19 MA_MD22 MA_MD23 MA_MD18 MA_MD24 MA_MD29 MA_MD25 MA_MD28 MA_DQS3- +V1.2DDR MIO-5373 User Manual...
  • Page 81 MA_DQS3+ MA_MD27 MA_MD26 MA_MD30 MA_MD31 MA_CB5 MA_CB4 MA_CB1 MA_CB0 MA_DQS8- +V1.2DDR MA_DQS8+ MA_CB6 MA_CB2 MA_CB7 MA_CB3 DDR4_DRAMRST# MA_CKE0 MA_CKE1 +V1.2DDR +V1.2DDR MA_BG1 MA_ACT# MA_BG0 DDR0_A_ALERT# +V1.2DDR +V1.2DDR MA_MA12 MA_MA11 MA_MA9 MA_MA7 +V1.2DDR MIO-5373 User Manual...
  • Page 82 +V1.2DDR MA_MA3 MA_MA2 MA_MA1 DDR0_A_EVENT# +V1.2DDR +V1.2DDR MA_CLK_DDRA0+ MA_CLK_DDRA1+ MA_CLK_DDRA0- MA_CLK_DDRA1- +V1.2DDR +V1.2DDR DDR0_A_PARITY MA_MA0 MA_BA1 MA_MA10 +V1.2DDR +V1.2DDR MA_SCS#0 MA_BA0 MA_SWE# MA_SRAS# +V1.2DDR +V1.2DDR MA_ODT0 MA_SCAS# MA_SCS#1 MA_MA13 +V1.2DDR +V1.2DDR MA_ODT1 +V1.2DDR DDR0_VREF_Z_CA DIMMA_SA2 MA_MD33 MA_MD36 MIO-5373 User Manual...
  • Page 83 MA_MD37 MA_MD32 MA_DQS4- +V1.2DDR MA_DQS4+ MA_MD35 MA_MD38 MA_MD34 MA_MD39 MA_MD40 MA_MD44 MA_MD45 MA_MD41 MA_DQS5- +V1.2DDR MA_DQS5+ MA_MD43 MA_MD47 MA_MD46 MA_MD42 MA_MD50 MA_MD48 MA_MD52 MA_MD49 MA_DQS6- MIO-5373 User Manual...
  • Page 84 +V1.2DDR MA_DQS6+ MA_MD53 MA_MD54 MA_MD55 MA_MD51 MA_MD56 MA_MD57 MA_MD60 MA_MD61 MA_DQS7- +V1.2DDR MA_DQS7+ MA MD62 MA MD59 MA MD58 MA MD63 SMB_CLK SMB OAT +V3.3 DIMMA_SAO +V2.5_VPP +V0.6 VTT +V2.5 VPP DIMMA_SA1 MIO-5373 User Manual...

  • Page 85: Gpio/Rs232 Connector

    A.3.14GPIO/RS232 Connector Signal Pin Definition GPIO7/COM_RI# GPIO2/COM_DTR# GPIO6/COM_CTS# GPIO1/COM_TXD GPIO5/COM_RTS# GPIO0/COM_RXD GPIO4/COM_DSR# +V5_GPIO/COM_DCD# GPIO3/COM_GND MIO-5373 User Manual...

  • Page 86: Gpio/Rs232 Connector

    A.3.15GPIO/RS232 Connector Signal Pin Definition GPIO7/COM_RI# GPIO2_COM_DTR# GPIO6/COM_CTS# GPIO1/COM_TXD GPIO5/COM_RTS# GPIO0/COM_RXD GPIO4/COM_DSR# +V5_GPIO/COM_DCD# GPIO3/COM_GND A.3.16COM port Connector (RS232+RS422+RS485) Signal Pin Definition 422RX-/DTR# CTS# 422RX+/TXD RTS# 422TX+/485D+/RXD DSR# 422TX-/485D-/DCD# MIO-5373 User Manual...

  • Page 87: Power/Led/Case Open/Buzzer Connector

    A.3.17Power/LED/Case Open/Buzzer Connector Signal Pin Definition BUZZER- BUZZER+ CASEOPEN SATA_LED# PSIN# RST# +3.3V A.3.18Audio Connector Signal Pin Definition LOUTR LINR LOUTL LINL MIC1R MIC1L MIO-5373 User Manual...

  • Page 88: Hdd Power Connector

    A.3.19HDD Power Connector Signal Pin Definition A.3.20HDD Connector Signal Pin Definition SATA0_TX+ SATA0_TX- SATA0_RX- SATA0_RX+ MIO-5373 User Manual...

  • Page 89: Hdd Connector

    A.3.21HDD Connector Signal Pin Definition SATA1_TX+ SATA1_TX- SATA1_RX- SATA1_RX+ A.3.22LVDS Connector Signal Pin Definition +V_LCD +V_LCD +V_LCD +V_LCD LVDS1_0_D0- LVDS1_1_D0- LVDS1_0_D0+ LVDS1_1_D0+ MIO-5373 User Manual...
  • Page 90 LVDS1_0_D1- LVDS1_1_D1- LVDS1_0_D1+ LVDS1_1_D1+ LVDS1_0_D2- LVDS1_1_D2- LVDS1_0_D2+ LVDS1_1_D2+ LVDS1_0_CLK- LVDS1_1_CLK- LVDS1_0_CLK+ LVDS1_1_CLK+ LVDS1_0_D3- LVDS1_1_D3- LVDS1_0_D3+ LVDS1_1_D3+ LVDS1_VCON MIO-5373 User Manual...

  • Page 91: Panel Inverter Connector

    A.3.23Panel Inverter Connector Signal Pin Definition +V12 LVDS1_ENABKL LVDS1_PWM A.3.24SIM card Connector Signal Pin Definition +VUIM_PWR UIM RESET UIM_CLK +VUIM_VPP UIM DATA SIM_DET MIO-5373 User Manual...

  • Page 92: Key M And Key B Connector

    PCIE_KEY-M_R_RX9+ USB7_P+ WWAN_DISABLE# WWAN_DISABLE# USB7_KEYB_P- PCIE_A_PCH_TXN3 +V3.3_M.2 PCIE_A_PCH_TXP3 +V3.3_M.2 B Key NC +V3.3_M.2 PCIE_KEY-M_RX8- +V3.3_M.2 PCIE_KEY-M_RX8+ M.2_CONFIG_0 (GND) M.2_CONFIG_0 PCIE_A_PCH_TXN2 PCIE_A_PCH_TXN2 PCIE_A_PCH_TXP2 PCIE_A_PCH_TXP2 PCIE_KEY-M_RX7- PCIE_KEY-M_RX7- UIM_A_RESET UIM_A_RESET PCIE_KEY-M_RX7+ PCIE_KEY-M_RX7+ UIM_A_CLK UIM_A_CLK UIM_A_DATA UIM_A_DATA PCIE_A_PCH_TXN1 PCIE_A_PCH_TXN1 +VUIM_A_PWR +VUIM_A_PWR MIO-5373 User Manual...
  • Page 93 PCIE_A_PCH_TXP1 PCIE_A_PCH_TXP1 MPCIE_MSATA_RX+ MPCIE_MSATA_RX+ MPCIE_MSATA_RX- MPCIE_MSATA_RX- MPCIE_MSATA_TX- MPCIE_MSATA_TX- MPCIE_MSATA_TX+ MPCIE_MSATA_TX+ PLTRST_MKEY_BUFFER# CLK2_M2MB_A_PCIE_REQ# CLK2_M2MB_A_PCIE_REQ# CK_100M_A_MKEY_N CK_100M_A_MKEY_N M.2_PCIE_WAKE# M.2_PCIE_WAKE# CK_100M_A_MKEY_P CK_100M_A_MKEY_P M Key NC SIM_KEYB_DET M.2_RESET#_R M.2_RESET#_R PCH_SUSCLK_R_MKEY PCH_SUSCLK_R_MKEY M2_SSD_PEDET M2_SSD_PEDET +V3.3_M.2 +V3.3_M.2 +V3.3_M.2 +V3.3_M.2 +V3.3_M.2 +V3.3_M.2 MIO-5373 User Manual...

  • Page 94: Key E Connector

    A.3.26Key E Connector Signal Pin Definition (Key E) +V3.3SB_M.2_E USB6 Z P+ +V3.3SB_M.2_E USB6_Z_P- MIO-5373 User Manual...
  • Page 95 E Key NC PCIE_M2_Z_TX7+ PCIE_M2_Z_TX7- PCIE_M2_RX7+ PCIE_M2_RX7- CLK_M2E_Z_PCIE+ CLK_M2E_Z_PCIE- SUSCLK_Z_EKEY PLTRST_BUFFER# PCIE_A_CLKREQ2# BT_DISABLE# PCIE_WAKE# WIFI_DISABLE# I2C0_KEYE_DAT I2C0_KEYE_CLK MIO-5373 User Manual...

  • Page 96: Rtc Battery Connector

    +V3.3SB_M.2_E +V3.3SB_M.2_E A.3.27RTC Battery Connector Signal Pin Definition (Key M) +VBAT A.3.28eDP Connector MIO-5373 User Manual...
  • Page 97 Signal Pin Definition EDP_Z_TX3- EDP_Z_TX3+ EDP_Z_TX2- EDP_Z_TX2+ EDP_Z_TX1- EDP_Z_TX1+ EDP_Z_TXO- EDP_Z_TXO+ EDP_Z_AUX+ EDP_Z_AUX- +V_LCD +V_LCD +V_LCD +V_LCD MIO-5373 User Manual...

  • Page 98: Mioe Connector

    DDP3_EDP_Z_HPD LVDS1_z_ENABKL EC_LVDS1_z_PWM +V12_+V5_EDP_INVERTER_O +V12_+V5_EDP_INVERTER_O +V12_+V5_EDP_INVERTER 0 +V12_+V5_EDP_INVERTER_O A.3.29MIOe Connector MIO-5373 User Manual...
  • Page 99 Signal Pin Definition (Key M) PCIE_MIO_RX1+ PCIE_MIO_A_TX1+ PCIE_MIO_RX1- PCIE_MIO_A_TX1- PCIE_MIO_RX2+ PCIE_MIO_A_TX2+ PCIE_MIO_RX2- PCIE_MIO_A_TX2- PCIE_MIO_RX3+ PCIE_MIO_A_TX3+ PCIE_MIO_RX3- PCIE_MIO_A_TX3- PCIE_MIO_RX4+ PCIE_MIO_A_TX4+ PCIE_MIO_RX4- PCIE_MIO_A_TX4- CLK5_PCIE_MIO+ LOUTL_MIO CLK5_PCIE_MIO- LOUTR_MIO SMB_STB_CLK SMB_STB_DAT PCIE_WAKE# PLTRST_BUFFER# PM_SLP_S3# CLKOUT_MIO LPC_AD0 LPC_AD1 MIO-5373 User Manual...
  • Page 100 LPC_AD2 LPC_AD3 LPC_SERIRQ LPC_FRAME# USB5_P+ USB5_P- USB5_OC#3 +V12SB_MIO +V12SB_MIO +V5SB +V5SB +V5SB +V5SB MIO-5373 User Manual...

  • Page 101: Canbus Connector

    A.3.30CANBus Connector Name Net Name CAN1_D+ CAN1_D- MIO-5373 User Manual...
  • Page 102 MIO-5373 User Manual...

  • Page 103: Appendix B System Assignments

    Appendix System Assignments This appendix contains informa- tion of a detailed nature.  System I/O Ports  DMA Channel Assignments  First MB Memory Map  Interrupt Assignments...

  • Page 104: System I/O Ports

    Table B.3: First MB Memory Map Addr. Range (Hex) Device E0000h - FFFFFh System board D0000h - DFFFFh PCI Bus C0000h - CFFFFh System board A0000h - BFFFFh PCI Bus A0000h - BFFFFh ® Intel HD Graphic 00000h - 9FFFFh System board MIO-5373 User Manual...

  • Page 105: Interrupt Assignments

    Communications port (COM2) IRQ4 Communications port (COM1) IRQ5 EC Watch DOG IRQ6 Available IRQ7 Available IRQ8 System CMOS/real time clock IRQ9 Microsoft ACPI-compliant system IRQ10 Available IRQ11 SATA controller IRQ12 Available IRQ13 Numeric data processor IRQ14 Reserved IRQ15 Reserved MIO-5373 User Manual...
  • Page 106 MIO-5373 User Manual...

  • Page 107: Appendix C Watchdog Timer Sample Code

    Appendix Watchdog Timer Sample Code...

  • Page 108: Watchdog Timer Sample Code

    EC_Data_Port mov al, 30h ; Set 3 seconds delay time. out dx,al mov dx, EC_Command_Port mov al, 89h ; Write EC HW ram. out dx,al mov dx, EC_Data_Port mov al,57h ; Watch dog event flag. out dx,al MIO-5373 User Manual...
  • Page 109 EC_Data_Port mov al, 04h ; Reset event. out dx,al mov dx, EC_Command_Port mov al,28h ; start WDT function. (stop: 0x29, reset: 0x2A) out dx,al .exit MIO-5373 User Manual...
  • Page 110 No part of this publication may be reproduced in any form or by any means, such as electronically, by photocopying, recording, or otherwise, without prior written permission from the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd. 2020...

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