Related Manuals for Advantech MIC-3396
Summary of Contents for Advantech MIC-3396
- Page 1 User Manual MIC-3396 6U CompactPCI 4th Generation ® Intel Core™ i3/i5/i7 Processor Blade with ECC support...
- Page 2 No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable. How- ever, Advantech Co., Ltd.
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Page 3: Declaration Of Conformity
Class I, Division 2, Groups A, B, C and D indoor hazards. Technical Support and Assistance Visit the Advantech website at http://support.advantech.com where you can find the latest information about the product. Contact your distributor, sales representative, or Advantech's customer service center for technical support if you need additional assistance. -
Page 4: Packing List
Before setting up the system, check that the items listed below are included and in good condition. If any item is not accord with the table, please contact your dealer immediately. MIC-3396 all-in-one single board computer (CPU heatsink and PCH heatsink included) x1 Daughter board for SATA HDD x1(Assembled) ... -
Page 5: Safety Instructions
The sound pressure level at the operator's position according to IEC 704-1:1982 is no more than 70 dB (A). DISCLAIMER: This set of instructions is given according to IEC 704-1. Advantech disclaims all responsibility for the accuracy of any statements contained herein. - Page 6 We Appreciate Your Input Please let us know of any aspect of this product, including the manual, which could use improvement or correction. We appreciate your valuable input in helping make our products better. MIC-3396 User Manual...
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Page 7: Table Of Contents
Table 1.12: SW5 & SW6 for COM2 ..........12 Connector Definitions................13 Table 1.13: MIC-3396 connector descriptions......13 Figure 1.2 MIC-3396 Front Panel Ports, Indicators and Buttons13 Figure 1.3 RIO-3316-C1E Front Panel Ports and Indicators ..13 1.5.1 USB Connectors ................. 13 1.5.2... - Page 8 Installation Steps..................15 1.7.1 HDD Installation Steps..............15 Figure 1.4 Complete assembly of MIC-3396 ......15 Figure 1.5 Fasten screws on the SATA HDD bracket ....16 Figure 1.6 Introduce SATA HDD into SATA connector ..... 16 Battery Replacement ................17 Software Support ..................
- Page 9 Figure 2.40Security Setting ............51 2.3.7 Save & Exit Option..............52 Figure 2.41Save and Exit ............52 Chapter IPMI for the MIC-3396 ......53 Introduction ..................... 54 Terms and Definitions ................54 IPMI Interfaces ..................55 Figure 3.1 Management part block diagram ......55 3.3.1...
- Page 10 M/D, PWR, BMC, HDD and Hot-swap LEDs ......79 Appendix B Programming the Watchdog Timer . 81 Appendix C FPGA ..........83 Overview ....................84 Features....................84 FPGA I/O Registers ................84 Table C.1: LPC I/O registers address ........84 Appendix D Glossary..........85 MIC-3396 User Manual...
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Page 11: Chapter 1 Hardware Configuration
Chapter Hardware Configuration This chapter describes how to configure MIC-3396 hardware... -
Page 12: Introduction
The MIC-3396 is compliant with PICMG 2.0 Rev. 3.0. It supports a 64-bit / 66 MHz or 33MHz PCI bus for up to 7 CompactPCI slots at 3.3 V or 5 V VIO. The MIC-3396 is hot-swap compliant (PICMG 2.1) and conforms to the CompactPCI Packet Switching Backplane specification (PICMG 2.16) as well as the CompactPCI System Manage-... -
Page 13: Processor
1.2.6 Memory The MIC-3396 has up to 8 GB of onboard with ECC support DDR3L memory. It also has one 240-pin SO-DIMM socket that can accommodate an additional 2GB (max. to 8GB) of memory. The following table shows a list of SO-DIMM modules that have been tested on the MIC-3396. -
Page 14: Ethernet
1.2.8 Storage Interface The MIC-3396 supports six SATA III interfaces. One SATA III interface is routed to an onboard 2.5" SATA hard disk drive; one is routed to support an on-board flash (optional); one is CFast connector; two are routed to the rear I/O module via the J3 connector. -
Page 15: Watchdog Timer
1.2.13 Optional Rear I/O Modules The RIO-3316 is the optional RTM (also known as rear I/O module) for the MIC-3396. It offers a wide variety of I/O features, such as two or four RJ45 LAN ports, two COM ports, two DVI ports, one USB3.0, one USB2.0 port, one P/S2 port. RIO-3316-D1E can carrier an on-board 2.5”... -
Page 16: Compactpci Bridge
Please consult the Pericom PI7C9X130D data book for details. 1.2.17 I/O Connectivity For MIC-3396, the front panel I/O is provided by two RJ-45 Gigabit Ethernet ports, one RJ-45 COM port, two USB 3.0 and one USB 2.0 ports, one VGA connector, and one XMC/PMC knockout. -
Page 17: Hardware Monitor
The PS2 (keyboard/mouse) is routed to the rear I/O module. 1.2.21 RTC and Battery The RTC module keeps the date and time. On the MIC-3396 model the RTC circuitry is connected to battery sources (CR2032M1S8-LF, 3V, 210mAH). 1.2.22 IPMI The MIC-3396 uses the Intelligent Platform Management Interface (IPMI) to monitor the health of an entire system. -
Page 18: Jumpers And Switches
Jumpers and Switches Table 1.4 and table 1.5 list the jumper and switch functions. Read this section care- fully before changing the jumper and switch settings on your MIC-3396 board. Table 1.4: MIC-3396 jumper descriptions Number Function Clear CMOS Switch VGA output to front panel or to rear Table 1.5: MIC-3396 switch descriptions... -
Page 19: Vga Output (Jp5)
1.4.2 VGA Output (JP5) This jumper is used to switch VGA output from front panel to rear. Table 1.7: JP5 Default Front Panel Rear IO MIC-3396 User Manual... -
Page 20: Switch Settings
1.4.3 Switch Settings ■ represents the key Note! Table 1.8: SW1-1 PCI Bridge Master/Drone Mode Default Master Mode Drone Mode Table 1.9: SW1-2 DRONE_PCISRT#_SW Default Drone Mode w/o J1 RST Drone Mode w/ J1 RST MIC-3396 User Manual... -
Page 21: For Bmc/Sio Uart
RTM COM1 for BMC RTM COM2 for SIO COM2 Front COM for SIO COM2 RTM COM1 for SIO COM1 RTM COM2 for BMC 1.4.4 RIO-3316-C1E DIP Switch Setting Table 1.11: SW3 & SW4 for Internal COM1 Default RS232 RS422 RS485 MIC-3396 User Manual... -
Page 22: Table 1.12: Sw5 & Sw6 For Com2
Table 1.12: SW5 & SW6 for COM2 Default RS232 RS422 RS485 These switches are only available for the RIO-3316-C1E model. MIC-3396 User Manual... -
Page 23: Connector Definitions
Serial Bus (USB) 3.0 channels. Two USB 3.0 and one USB 2.0 ports are on the front panel of MIC-3396. Four other USB 2.0 and one other USB 3.0 channels are routed to rear I/O via the J3/J5 connector. One USB2.0 and one USB3.0 ports are on the front panel of RIO-3316-C1E, the other three are on-board connectors. -
Page 24: Serial Ports
The MIC-3396 provides one serial port and the RIO-3316 provides two serial ports. The serial port is available as RS-232 interfaces via RJ-45 connectors on the front panel of MIC-3396. An RJ-45 to DB-9 adaptor cable is provided in the MIC-3396 accessories to facilitate connectivity to external console or modem devices. The BIOS Advanced Setup program covered in Chapter 2 provides a user interface for features such as enabling or disabling the ports and setting the port address. -
Page 25: Installation Steps
1.7.1 HDD Installation Steps The MIC-3396 supports 2.5” SATA hard disk drive. The SATA HDD daughter board is assembled on the MIC-3396, but the SATA HDD brackets are not assembled on the MIC-3396. The brackets and screws are packed as accessories in the package. Fol- lowing steps illustrate the installation of the SATA HDD. -
Page 26: Figure 1.5 Fasten Screws On The Sata Hdd Bracket
Align the HDD bracket on the side of HDD and fasten 4pcs M2.5 screw on the on the bracket. Figure 1.5 Fasten screws on the SATA HDD bracket Put the SATA HDD with bracket on the post and introduce SATA HDD into SATA connector. Figure 1.6 Introduce SATA HDD into SATA connector MIC-3396 User Manual... -
Page 27: Battery Replacement
Software Support Windows 7, Windows 8, Windows 2008 Enterprise R2 SP1, VxWorks 6.8/6.9 and RHEL 6.4 have been fully tested on the MIC-3396. Please contact your local sales representative for details on support for other operating systems. MIC-3396 User Manual... - Page 28 MIC-3396 User Manual...
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Page 29: Chapter 2 Ami Bios Setup
Chapter AMI BIOS Setup This chapter describes how to configure the AMI BIOS. -
Page 30: Introduction
The AMI BIOS has been customized and integrated into many industrial and embed- ded motherboards for decades. This section describes the BIOS which has been specifically adapted for the MIC-3396. With the AMI UEFI BIOS Setup Utility, you can modify BIOS settings and control the special features of the MIC-3396. The Setup program uses a number of menus for making changes and turning the special fea- tures on or off. -
Page 31: Bios Setup
BIOS Setup The MIC-3396 Series system has AMI BIOS built in, with a CMOS SETUP utility that allows users to configure required settings or to activate certain system features. The CMOS SETUP saves the configuration in the CMOS RAM of the motherboard. -
Page 32: Main Setup
System Date using the <Arrow> keys. Enter new values through the keyboard. Press the <Tab> key or the <Arrow> keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. MIC-3396 User Manual... -
Page 33: Advanced Bios Features Setup
2.3.2 Advanced BIOS Features Setup Select the Advanced tab from the MIC-3396 setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the <Arrow>... -
Page 34: Figure 2.4 Pci Setting
Maximum Payload Set Maximum Payload of PCI Express Device or allow System BIOS to select the value. Maximum Read Request Set Maximum Read Request Size of PCI Express Device or allow system BIOS to select the value. MIC-3396 User Manual... -
Page 35: Figure 2.5 Acpi Settings
Enable Hibernation Enable or Disable System Hibernation (OS/S4 Sleep State). This option may be not effective with some OS. ACPI Sleep State Select the ACPI sleep state the system will enter when the SUSPEND button is pressed. MIC-3396 User Manual... -
Page 36: Figure 2.6 Trusted Computing
Figure 2.6 Trusted Computing Trusted Computing settings Enable/Disable Trusted Computing Enables or Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available. 2.3.2.4 CPU Configuration MIC-3396 User Manual... -
Page 37: Figure 2.7 Cpu Configuration
This item allows users to enable or disable the adjacent cache line prefetcher feature. EIST This item allows users to enable or disable Intel SpeedStep. CPU C States This item allows users to enable or disable CPU C states. MIC-3396 User Manual... -
Page 38: Figure 2.8 Sata Configuration
Intel TXT(LT) support Enables or Disables Intel® TXT (LT) support. 2.3.2.5 SATA Configuration Figure 2.8 SATA configuration SATA Controller This items allow users to enable or disable SATA function. [Disabled] Disable SATA function. MIC-3396 User Manual... - Page 39 RAID mode Set to [RAID mode] when you want the SATA hard disk drives to use the RAID mode. The Intel RAID function allows the user to build up RAID0 or RAID1. MIC-3396 User Manual...
- Page 40 Press "Ctrl + I" into Intel® Rapid Storage Technology - Option ROM Choose "Create RAID Volume" to build RAID0 or RAID1. MIC-3396 User Manual...
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Page 41: Figure 2.9 Raid Mode
Disable option will keep USB device available only for EFI applications USB3.0 support Enable or disable USB3.0 (XHCI) Controller support XHCI Hand-off This is a workaround for OSes without XHCI hand-off support. MIC-3396 User Manual... -
Page 42: Figure 2.11Super Io Configurations
USB mass storage device start unit command time out. Device power-up delay Maximum time the device will take before it properly reports itself to the host controller. 2.3.2.7 Super I/O Configuration Figure 2.11 Super IO Configurations MIC-3396 User Manual... -
Page 43: Figure 2.12Serial Port 0/1 Configurations
Serial Port 0/1 Configuration For serial port 0/1, IRQ/IO mode resource configuration, users can choose IRQ, IO and MODE. Figure 2.12 Serial Port 0/1 Configurations MIC-3396 User Manual... -
Page 44: Figure 2.13Pc Health Status
2.3.2.8 H/W Monitor Configuration System temperature, CPU temperature and voltage status can be checked in PC Health Status. Figure 2.13 PC Health Status 2.3.2.9 Serial Port Console Redirection Setting Figure 2.14 Console redirection Settings MIC-3396 User Manual... -
Page 45: Figure 2.15Out-Of-Band Mgmt Port
Select the port for Microsoft Windows Emergency Management Services (EMS) to allow for remote management of a Windows Server OS. Figure 2.16 Terminal Type Terminal Type VT-UTF8 is the preferred terminal type for out-of-band management. The next best choice is VT100+ and then VT100. MIC-3396 User Manual... -
Page 46: Figure 2.17Network Stack
2.3.2.10 Network Stack Figure 2.17 Network Stack Network Stack This item allows users to enable or disable UEFI network stack. MIC-3396 User Manual... -
Page 47: Figure 2.18Nic Configuration Settings
Configure Boot Protocol, Wake on LAN, Link Speed, and VLAN. Figure 2.19 Link Speed Link Speed Specifies the port speed used for the selected boot protocol. Wake On LAN This item allows users to enable the server to be powered on. MIC-3396 User Manual... -
Page 48: Figure 2.20Nic Configuration Settings
Configure Boot Protocol, Wake on LAN, Link Speed, and VLAN. Figure 2.21 Link Speed Link Speed Specifies the port speed used for the selected boot protocol. Wake On LAN This item allows users to enable the server to be powered on. MIC-3396 User Manual... -
Page 49: Chipset Configuration Setting
<Arrow> keys. All Chipset Setup options are described in this section. The Chipset Setup screens are shown below. The sub menus are described on the following pages. Figure 2.22 Chipset Configuration Settings 2.3.3.1 North Bridge Configuration VT-d Capability Figure 2.23 VT-d MIC-3396 User Manual... -
Page 50: Figure 2.24Graphics Configuration
This item allows users to select DVMT 5.0 Pre-Allocated (fixed) Graphics mem- ory size used by the internal graphics device. – DVMT Total Gfx Mem This item allows users to select DVMT5.0 total Graphic memory size used by the internal graphic device. MIC-3396 User Manual... -
Page 51: Figure 2.25Lcd Control
POST. This has no effect if external graphics present. Secondary boot display selection will appear based on your selection. – LCD Panel Type This item allows users to select panel resolution. – Panel Scaling This item allows users to enable or disable panel scaling. MIC-3396 User Manual... -
Page 52: Figure 2.26Nb Pcie Configuration
NB PCIe Configuration Figure 2.26 NB PCIe Configuration – PEG0 - Gen x Select PEG0 speed. – Enabled PEG This item allows users to enable or disable PEG. Memory Configuration MIC-3396 User Manual... -
Page 53: Figure 2.27Memory Configuration
Figure 2.27 Memory Configuration 2.3.3.2 South Bridge Configuration PCI Express Configuration Settings Allow enable or disable PCI Express Root Port Figure 2.28 PCI Express Configuration MIC-3396 User Manual... -
Page 54: Figure 2.29Usb Configuration
USB Configuration Figure 2.29 USB Configuration Mode of operation of xHCI controller allows user to enable or disable USB port. PCH Azalia Configuration Figure 2.30 PCH Azalia Configuration Control Detection of the Azalia device. MIC-3396 User Manual... -
Page 55: Boot Configuration
NumLock state will stay "OFF" after booting. Boot Option Priority Boot Option #1 Boot Option #2 Show the boot device choices. Hard Drive BBS Priorities Select the main hard disk device type to be a boot hard drive. MIC-3396 User Manual... -
Page 56: Figure 2.32Hard Drive Bbs Priorities
Figure 2.32 Hard Drive BBS Priorities CSM16 Parameters Figure 2.33 CSM16 Parameters This item allows users to set display mode for Option ROM. MIC-3396 User Manual... -
Page 57: Figure 2.34Csm Parameters
This option controls if CSM will be launched. 2.3.5 PXE Boot Setting Enter into Boot setting and choose CSM parameters. Launch PXE OpROM policy Figure 2.35 Launch PXE OpROM policy Choose "Legacy only" or "UEFI only" for launch PXE OpROM policy. MIC-3396 User Manual... -
Page 58: Figure 2.36Save And Exit
Save and Exit Figure 2.36 Save and Exit Choose boot option priority The "Network device BBS Priorities" will be shown after enabled PXE OpROM. MIC-3396 User Manual... -
Page 59: Figure 2.37Boot Option Priority
Note 1: Network Device BBS Priorities Note 2: Hard Drive BBS Priorities Figure 2.37 Boot option priority MIC-3396 User Manual... -
Page 60: Figure 2.38Save Changes And Reset
Save Changes and Reset again Figure 2.38 Save changes and reset Start PXE Server Figure 2.39 Start page of PXE Server MIC-3396 User Manual... -
Page 61: Security Setting
Select this option and press <ENTER> to access the sub menu, and then type in the password. Set the Administrator password. User Password Select this option and press <ENTER> to access the sub menu, and then type in the password. Set the User Password. MIC-3396 User Manual... -
Page 62: Save & Exit Option
Select Restore Defaults from the Exit menu and press <Enter>. Save as User Default Save the all current settings as a user default. Restore User Default Restore all settings to user default values. Boot Override Show the boot device types on the system. MIC-3396 User Manual... -
Page 63: Chapter 3 Ipmi For The Mic-3396
Chapter IPMI for the MIC-3396 This chapter describes IPMI con- figuration for the MIC-3396. -
Page 64: Introduction
Introduction The MIC-3396 fully supports the major IPMI 2.0 interface and the PICMG 2.9 R1.0 specification. The BMC solution is based on the Advantech IPMI Core G02 and it is designed around a combination of a NXP LPC1768 ARM Cortex-M3 based 32 bit microcontroller and a Lattice MachXO2 series FPGA. -
Page 65: Ipmi Interfaces
XMC mezzanine card (Vita 42.0) IPMI Interfaces The MIC-3396 provides three main IPMI messaging interfaces to connect to the BMC. There are the IPMB-0 for main messaging interface between CPCI boards, the LAN side band interface (NCSI) and the on-board payload interface to x86 (KCS). -
Page 66: Kcs
UDP in turn uses the IP protocol for data transport, so the network stack needs to support the IP and UDP protocols along with RMCP. RMCP+ was added in the IPMI v2.0 specification. It’s an enhanced protocol for trans- ferring IPMI messages and other types of payloads (e.g. serial data). MIC-3396 User Manual... -
Page 67: Command Line Interface
Command Line Interface The Advantech IPMI core supports besides the IPMI defined interfaces a command line interface to grant easy and fast human readable system information. This can be used for debugging and error recovery as well as showing information about the board and firmware status. -
Page 68: System Event Log (Sel)
BMC Watchdog sensor FW Progress sensor Version change sensor Advantech OEM Sensor: Integrity Sensor 3.7.1 Sensor List The following table specifies all sensors provided by the BMC: Table 3.3: BMC sensor list Sensor Type Sensor ID... -
Page 69: Threshold Based Sensors
1.62 1.71 1.89 1.98 2.02 AUX_3_3-VOL 3.30 2.90 3.00 3.15 3.45 3.60 3.70 HP_3_3-VOL 3.30 2.90 3.00 3.15 3.45 3.60 3.70 HP_5_0-VOL 5.00 4.40 4.50 4.75 5.25 5.50 5.60 HP_12_0-VOL 12.0 9.90 10.2 10.8 13.2 13.8 14.1 MIC-3396 User Manual... -
Page 70: Temperature Sensors
0xA0. Byte 2 satisfies the logical component, while byte 3 stands for its action. The table below shows the supported event code structure gen- erated by the integrity sensors on the MIC-3396. Table 3.7: Integrity Sensor event data table... -
Page 71: Oem Ipmi Commands
Advantech’s IANA Enterprise Number used for OEM commands is 002839h. The BMC supports all Advantech IPMI OEM commands listed in below table. Table 3.8: OEM command list Command... -
Page 72: Store Configuration Command
Port) are used to select the item that should be changed; the last byte contains the new setting value. Table 3.9: Store Configuration Settings Command byte data field Request Data Advantech IANA ID (392800h) Setting 00h - 02h = reserved 03h = Bios 04h = Lan controller 05h = Failure retries... - Page 73 01h = enabled Response Data Completion Code C7h = request data length invalid C9h = parameter out of range CBh = requested data not present D5h = not supported in present state Advantech IANA ID (392800h) Setting MIC-3396 User Manual...
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Page 74: Read Configuration Command
Port) are used to select the item that should be read out, the answer contains the set- ting value. Table 3.10: Read Configuration Settings Command byte data field Request Data Advantech IANA ID (392800h) Setting 00h – 02h = reserved 03h = Bios 04h = Lan controller 05h = Failure retries... - Page 75 04h = RTM 2 CLI: BMC UART Baudrate 00h = 9600 01h = 14400 02h = 19200 03h = 38400 04h = 57600 05h = 115200 IRQ: PROC hot IRQ enabled 00h = disabled 01h = enabled MIC-3396 User Manual...
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Page 76: Read Port 80 Command
This command is used to read out the actual POST code of the UEFI BIOS. Table 3.11: Read Port 80 command (BIOS POST code) byte data field Request Data Advantech IANA ID (392800h) Response Data Completion Code Advantech IANA ID (392800h) POST code 3.8.4... -
Page 77: Hpm.1 Upgrade Support
CompactPCI. The Advantech IPMI Core G02 supports HPM.1 updates over any of its IPMI inter- faces. See the following tables for a list of HPM.1 components implemented on the CPCI blade and their respective description. -
Page 78: Board Information
Board Information The BMC provides IPMI defined Field Replaceable Unit (FRU) information about the CPCI board and the connected extension modules. The MIC-3396 FRU data include general board information’s such as product name, HW version or serial number. A total of 2 kB non-volatile storage space is reserved for the FRU data. The boards IPMI FRU information can be made accessible via all BMC interfaces and the infor- mation can be retrieved at any time. -
Page 79: Product Information
Assert Tag type/length 0xC0 Assert Tag (unused) FRU File ID type/length 0xCB FRU File ID frudata.xml Custom product info area fields (unused) C1h (no more info fields) 0xC1 00h (any remaining unused space) 0x00 Product area checksum (calculated) MIC-3396 User Manual... - Page 80 MIC-3396 User Manual...
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Page 81: Appendix A Pin Assignments
Appendix Pin Assignments This appendix describes pin assignments. -
Page 82: J1 Connector
AD(22) AD(26) V(I/O) AD(25) AD(24) AD(30) AD(29) AD(28) AD(27) REQ0# PRESENT# 3.3V CLK0 AD(31) PCI_RST# GNT0# IPMB_PWR HEALTHY# V(I/O) INTP INTS INTA# INTB# INTC# INTD# TRST# － 12V ＋ 12V NC: No Connection Note! #: Active Low MIC-3396 User Manual... -
Page 83: J2 Connector
AD(53) AD(59) V(IO) AD(58) AD(57) AD(63) AD(62) AD(61) AD(60) C/BE(5)# GND/64EN# V(I/O) C/BE(4)# PAR64 V(I/O) C/BE(7)# C/BE(6)# CLK4 GNT3# REQ4# GNT4# CLK2 CLK3 SYSEN# GNT2# REQ3# CLK1 REQ1# GNT1# REQ2# NC: No Connection Note! #: Active Low MIC-3396 User Manual... -
Page 84: J3 Connector
PCIE_RX15+ SATA4_TX+ SATA4_RX+ VCC3 SATA5_TX+ SATA5_RX+ SATA4_TX- SATA4_RX- VCC3 SATA5_TX- SATA5_RX- VCC3 MDIB1+ MDIB1- MDIB3+ MDIB3- MDIB0+ MDIB0- MDIB2+ MDIB2- MDIA1+ MDIA1- MDIA3+ MDIA3- MDIA0+ MDIA0- MDIA2+ MDIA2- SATA_LED# NC NC: No Connection Note! #: Active Low MIC-3396 User Manual... -
Page 85: J4 Connector
DDI2_PAIR2+ DDI2_PAIR2- DDI2_DDC_CLK GND DDI2_PAIR3+ DDI2_DDC_DAT GND DDI2_PAIR3- DDI2_HPD 12-14 AUDIO_GND MIC_L MIC_R LINE_JD LINEIN_L LINEOUT_L LINEIN_R LINEOUT_R TBD (LOUT_L) AUDIO_GND TBD (LOUT_R) DDI2_DVIPWR AUDIO_GND J4_GPIO1 NC (VBAT) J4_GPIO2 PRST# NC: No Connection Note! #: Active Low MIC-3396 User Manual... -
Page 86: J5 Connector
RTMB_LINK- 2.16B_LINK10 UART2_RTS ACT# ACT# 2.16B_LINK- GND COM1_RX# COM1_CTS# COM2_DCD# COM2_TX# ACT# GND COM1_TX# COM1_DSR# RTM_PRES# COM2_RTS# COM2_DTR# GND COM1_RTS# COM1_DTR# UART2_TXD COM2_CTS# COM2_RI# GND COM1_DCD# COM1_RI# UART2_RXD COM2_DSR# COM2_RX# NC: No Connection Note! #: Active Low MIC-3396 User Manual... -
Page 87: Other Connector
VPWR(+5V) MPRESENT# NC(+3.3V_AU PERX_P2 PERX_N2 PERX_P3 PERX_N3 VPWR(+5V) TBD_SDA PERX_P4 PERX_N4 PERX_P5 PERX_N5 VPWR(+5V) NC(MVMRO) TBD_SCLK PERX_P6 PERX_N6 PERX_P7 PERX_N7 FPGAIO1 CLK_100Mhz CLK_100Mhz# FPGAIO2 NC(WAKE#) NC(ROOT#) Table A.8: VGA1 Connector GREEN BLUE DDC_DATA DET# HSYNC VSYNC DDC_CLK MIC-3396 User Manual... -
Page 88: Table A.9: Com1 (Rj45) Connector
+5V (fused) +5V (fused) USBD0- USBD1- USBD1- USBD0+ USBD1+ USBD1+ SSRX- SSRX- SSRX+ SSRX+ SSTX- SSTX- SSTX+ SSTX+ Table A.11: BH1 CMOS battery BAT_VCC Table A.12: RJ45 LAN Connector LAN_0+ LAN_2- LAN_0- LAN_1- LAN_1+ LAN_3+ LAN_2+ LAN_3- MIC-3396 User Manual... -
Page 89: M/D, Pwr, Bmc, Hdd And Hot-Swap Leds
Indicates Master or Drone mode status PWR (Green) Indicates power status HDD (Yellow) Indicates BMC status (heart beat to indicate BMC active) Hot Swap (Blue) Indicates the board is ready to be hot-swapped. BMC (Green) Indicates BMC status MIC-3396 User Manual... - Page 90 MIC-3396 User Manual...
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Page 91: Appendix B Programming The Watchdog Timer
Appendix Programming the Watchdog Timer This appendix describes how to program the watchdog timer. - Page 92 50 GOSUB 2000 REM Your application task #2, 60 OUT &H443, data REM Reset the timer 70 X=INP (&H444) REM, Disable the watchdog timer 80 END 1000 REM Subroutine #1, your application task 1070 RETURN 2000 REM Subroutine #2, your application task 2090 RETURN MIC-3396 User Manual...
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Page 93: Fpga
Appendix FPGA This appendix describes FPGA configuration. -
Page 94: Overview
LPC1768, like I C or KCS. As the MIC-3396 will be available in versions both with and without the BMC, some functions will be implemented redundant inside the FPGA and BMC. If the BMC is populated, a simple register inside the FPGA is used to control the regarding function from the BMC. -
Page 95: Appendix D Glossary
Appendix Glossary... - Page 96 Reliability, Availability, Serviceability, Usability and Manageability Rear Input/Output RS-232 An Interface specified by Electronic Industries Alliance Real Time Clock Rear Transition Module Single Board Computer SDRAM Synchronous DRAM Small Form-factor Pluggable Serial Presence Detect SoftWare Ultra Low Voltage Extension Module MIC-3396 User Manual...
- Page 97 MIC-3396 User Manual...
- Page 98 No part of this publication may be reproduced in any form or by any means, electronic, photocopying, recording or otherwise, without prior written permis- sion of the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd. 2015...