Advantech PCIE-1760 User Manual page 13

5. Delay Pulse Generation: Using PCIE-1760 internal clock, you can generate a sin-
gle pulse after a specific period, starting from a trigger signal connecting to counter
gate input. For example, if you define the count equals to 3 (as figure below), a single
pulse will be generated after 3 pulses of internal clock signals pass, after a trigger
signal from counter gate becomes high.
Note! If the output signal logic high time or logic low time (see figure below) is
less than 100 μs, you cannot see the output signal. This is because
PCIE-1760 is equipped with photocouple component on PWM output
channel, and their response time is not fast enough to make the fre-
quency faster than 20 kHz.
5 PCIE-1760 User Manual