Advantech PCIE-1744 User Manual
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Advantech PCIE-1744 User Manual

Advantech PCIE-1744 User Manual

30 ms/s simultaneous 4-ch analog input pci express card
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PCIE-1744
30 MS/s Simultaneous
4-ch Analog Input PCI Express
Card
User Manual

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Summary of Contents for Advantech PCIE-1744

  • Page 1 PCIE-1744 30 MS/s Simultaneous 4-ch Analog Input PCI Express Card User Manual...
  • Page 2 No part of this man- ual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reli- able.
  • Page 3 Product Warranty (2 years) Advantech warrants to you, the original purchaser, that each of its prod- ucts will be free from defects in materials and workmanship for two years from the date of purchase. This warranty does not apply to any products which have been repaired or...
  • Page 4 This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. This kind of cable is available from Advantech. Please contact your local supplier for ordering information.

  • Page 5: Table Of Contents

    Device Setup & Configuration ........17 Figure 2.4:Device Manager with Installed Devices ..17 Device Testing..............18 Figure 2.5:The Device Test Dialog Box of PCIE-1744 ... 2.5.1 Testing the Analog Input Function ......18 Figure 2.6:Analog Input tab on the Device Test dialog...
  • Page 6 Internal A/D Sample Clock .......... 33 4.3.2 External A/D Sample Clock 0 ........33 4.3.3 External A/D Sample Clock 1 ........33 Figure 4.5:PCIE-1744 Sample Clock Sources ..... 33 Trigger Sources ............... 34 4.4.1 Software Trigger ............34 4.4.2 External Digital (TTL) Trigger ........34 4.4.3...
  • Page 7 Appendix C Register Structure & Format ....... 52 Overview ................ 52 Register Format ............... 52 Table C.1:PCIE-1744 register format (Part 1) ..... 53 Table C.2:PCIE-1744 register format (Part 2) ..... 54 Table C.3:PCIE-1744 register format (Part 3) ..... 55 Table C.4:PCIE-1744 register format (Part 4) ..... 57 A/D Single Value Acquisition.........
  • Page 8 Table C.19:Register for Reset DMA Start Channel to CH0 70 C.18 AD Channel n DATA- Read BASE+30,32..... 71 Table C.20:Register for AD Channel n DATA ... 71 C.19 DMA Request Selector- Write BASE+34....... 72 Table C.21:Register for DMA Request Selector ..72 PCIE-1744 User Manual viii...
  • Page 9 Introduction This chapter will provide information on the features of the PCIE-1744 card, a quick installation guide, and informa- tion on software and accessories. Sections include: • Features • Applications • Installation Guide • Software Overview • Device Drivers Programming Roadmap •...

  • Page 10: Chapter 1 Introduction

    Chapter 1 Introduction Thank you for buying the Advantech PCIE-1744. The PCIE-1744 is a simultaneous 4-channel analog input card with high sampling rates. It is an advanced-performance data acquisition card based on 32-bit PCI- express bus architecture. The maximum sampling rate of PCIE-1744 is up to 30 MS/s.

  • Page 11: 32-Bit Pci Bus Mastering Dma Data Transfer

    An external pacer can also be used for triggering by externally connected equipment. 1.1.4 Onboard FIFO Memory There is 32k of FIFO sample memory on PCIE-1744.. This is an impor- tant feature for faster data transfers and more predictable performance under Windows systems.

  • Page 12: Applications

    • Gamma Camera Imaging • CCD Camera Imaging • Video Digitizing 1.3 Installation Guide Before you install your PCIE-1744, please make sure you have the fol- lowing necessary components: • PCIE-1744 DA&C card • PCIE-1744 Startup Manual • Driver software Advantech DLL drivers (included in the companion CD-ROM) •...

  • Page 13: Figure 1.1:Installation Flow Chart

    Figure 1.1: Installation Flow Chart Chapter 1...

  • Page 14: Software Overview

    1.4 Software Overview Advantech offers a rich set of DLL drivers, third-party driver supports and application software to help fully utilize the functions of your PCIE- 1744 card: • Device Drivers (on the companion CD-ROM) • LabVIEW driver • WaveScan 1.4.1 Programming Choices for DA&C Cards...

  • Page 15: Device Drivers Programming Roadmap

    • C++ Builder For instructions on how to begin programming in each development tool, Advantech offers a Tutorial Chapter in the Device Drivers Manual for your reference. Please refer to the corresponding sections in this chapter of the Device Drivers Manual to begin your programming efforts. You can also look at the example source code provided for each programming tool..

  • Page 16: Programming With Device Drivers Function Library

    1.5.2 Programming with Device Drivers Function Library Advantech Device Drivers offers a rich function library to be utilized in various application programs. This function library consists of numerous APIs that support many development tools, such as Visual C++, Visual Basic, Delphi and C++ Builder.

  • Page 17: Accessories

    Advantech offers a complete set of accessory products to support the PCIE-1744. These accessories include: 1.6.1 Wiring Cables PCL-10901-1 is specially designed for PCIE-1744 to connect to the wir- ing board, ADAM-3909, for external synchronization signal sources, such as external triggers and/or clock signals.
  • Page 18 PCIE-1744 User Manual...
  • Page 19 Installation This chapter gives a package item checklist, proper instructions about unpacking and step-by-step procedures for both driver and card installation.. Sections include: • Unpacking • Driver Installation • Hardware Installation • Device Setup & Configuration • Device Testing...

  • Page 20: Chapter 2 Installation

    Chapter 2 Installation 2.1 Unpacking After receiving your PCIE-1744 package, please inspect its contents first. The package should contain the following items: PCIE-1744 Companion CD-ROM (DLL driver included) User Manual The PCIE-1744 harbors certain electronic components vulnerable to elec- trostatic discharge (ESD). ESD could easily damage the integrated cir- cuits and certain components if preventive measures are not carefully paid attention to.

  • Page 21: Driver Installation

    2.2 Driver Installation We recommend you to install the driver before you install any of the the PCIE-1744 into your system, since this will guarantee a smooth installa- tion process. The Advantech Device Drivers setup program for the PCIE-1744 is included on the companion CD-ROM that is shipped with your DA&C...

  • Page 22: Figure 2.2:Different Options For Driver Setup

    Figure 2.2: Different Options for Driver Setup For further information on driver-related issues, an online version of the Device Drivers Manual is available by accessing: Start/Programs/Advantech Automation/Device Manager/Device Driver's Manual PCIE-1744 User Manual...

  • Page 23: Hardware Installation

    2.3 Hardware Installation After the DLL driver installation is completed, you can now go on to install the PCIE-1744 in any PCI Express slot on your computer. It is rec- ommended that you refer to the computer’s user manual or related docu- mentation if you have any doubts.

  • Page 24: Figure 2.3:The Device Name Listed In The Device Man Ager

    After the PCIE-1744 is installed, you can verify whether it is properly installed on your system in Device Manager: Access Device Manager through: Start /Control Panel /System /Device Manager. The device name of card should be listed on the Device Manager tab on the System Property Page.

  • Page 25: Device Setup & Configuration

    Device Manager is a utility that allows you to setup, configure and test your device, and later store your settings on the system registry. These settings will be used when you call the APIs of Advantech Device Driv- ers. Setting Up and Configuring the Device...

  • Page 26: Device Testing

    Figure 2.5: The Device Test Dialog Box of PCIE-1744 In the Device Test dialog box, you are free to test various functions of PCIE-1744 on the analog input tab, functions on the other tabs are not supported for this model.

  • Page 27: Figure 2.6:Analog Input Tab On The Device Test Dialog Box

    Figure 2.6: Analog Input tab on the Device Test dialog box Chapter 2...
  • Page 28 PCIE-1744 User Manual...

  • Page 29: Signal Connections

    Signal Connections This chapter provides information about how to connect input signals to the PCIE-1744 via the I/O connectors. Sections include: • Overview • Switch and Jumper Settings • Signal Connections...

  • Page 30: Chapter 3 Signal Connections

    A good signal connection can avoid unnecessary and costly dam- age to your PC and other hardware devices. This chapter provides useful information about how to connect input signals to PCIE-1744 via the I/O connectors. 3.2 Switch and Jumper Settings The PCIE-1744 has one function switch and five jumper settings.

  • Page 31: Boardid Switch Setting (Sw1)

    BoardID settings are used to set a board’s unique identifier when multiple identical cards are installed in the same system. The PCIE-1744 has a built-in DIP switch (SW1), which is used to define each card’s unique identifier. You can determine the unique identifier in the register as shown in following table.

  • Page 32: Power On Configuration After Hot Reset (Jp1)

    3.2.2 Power on Configuration after Hot Reset (JP1) Use JP1 to set the hot reset type of PCIE-1744. Power on configuration after hot reset Keep the hardware register setting after hot reset. Load the hardware register default setting after hot reset. (Default setting) 3.2.3 Input Terminator Select (JP2 to JP5)

  • Page 33: Signal Connections

    3.3 Signal Connections 3.3.1 Pin Assignments The pin assignments for the PS-2 connector and the DB9 connector are shown below. Table 3.1: PS-2 Pin Assignments Description EXT TRIG 0 EXT CLK 0+ EXT CLK 0- EXT CLK 1 Table 3.2: DB9 Pin Assignments Description EXT TRIG 0 EXT CLK 0+...
  • Page 34 PCIE-1744 User Manual...
  • Page 35 Operation This chapter describes the following features of the PCIE-1744 card: • Analog input ranges and gains • Analog input acquisition modes • A/D sample clock sources • Trigger sources • Analog Input Data Format...

  • Page 36: Chapter 4 Operation

    Chapter 4 Operation 4.1 Analog Input Ranges and Gains Each channel on the PCIE-1744 can measure bipolar analog input signals ranging within ± 5 V FSR, and can be set up with different input ranges respectively. The sampling rate can be up to 30 MS/s.

  • Page 37: Pacer Acquisition Mode

    4.2.3 Post-Trigger Acquisition Mode Post-trigger allows you to acquire data based on a trigger event. Posttrig- ger acquisition starts when the PCIE-1744 detects the trigger event and stop when the preset number of post-trigger samples has been acquired or when you stop the operation. This trigger mode must work with the DMA data transfer mode enabled.

  • Page 38: Delay Trigger Acquisition Mode

    The delay number of sample ranges from 2 to 65535 as defined in DMA counter. Delay-trigger acquisition starts when the PCIE-1744 detects the trigger event and stop when the specified number of A/D samples has been acquired or when you stop the operation.

  • Page 39: About Trigger Acquisition Mode

    Once a trigger event happens, the on-going data acquisition will continue until the designated amount of samples have been reached. When the PCIE-1744 detects the selected about trigger event, the card keeps acquiring the preset number of samples, and keeps the total number of samples on the FIFO.

  • Page 40: Pre-Trigger Acquisition Mode

    N+2. Figure 4.4: Pre-Trigger Acquisition Mode 4.3 A/D Sample Clock Sources The PCIE-1744 can adopt both internal and external clock sources for pacer, post-trigger, delay-trigger, about-trigger acquisition modes: • Internal A/D sample clock with 8-bit divider • External A/D sample clock that is connected to either the EXT-CLK0 (the differential clock source) or the EXT_CLK1 (the single ended clock source) on the ADAM-3909 screw terminal board.

  • Page 41: Internal A/D Sample Clock

    The external sample clock 0 is a sine wave signal source which is con- verted to a TTL signal inside the PCIE-1744. This signal is AC coupled. The input impedance of the external clock 0 is 50 ohms and the input level is 5 volts peak-to-peak.

  • Page 42: Trigger Sources

    4.4.2 External Digital (TTL) Trigger For analog input operations, an external digital trigger event occurs when the PCIE-1744 detects either a rising or falling edge on the External A/D TTL trigger input signal from screw terminal EXT_TRIG on the ADAM- 3909 screw terminal board.

  • Page 43: Analog Threshold Trigger

    TS0 to TS2 of Write/Read BASE+Eh. On the PCIE-1744 the analog trigger threshold voltage level is set using a dedicated 8-bit DAC; you can write or read the flags from AT0 to AT7 on Write/Read BASE+24h to define or identify the analog trigger threshold voltage level.

  • Page 44: Analog Input Data Format

    A/D Code Mapping Voltage Hex. Dec. 000h 7FFh 2047d -1 LSB 800h 2048d FFFh 2095d FS-1 LSB 1LSB FS/2048 Table 4.3: Corresponding Full Scale Values for Various Input Volt- age Ranges Gain Range ±5 ±2.5 ±1 ±0.5 PCIE-1744 User Manual...
  • Page 45 Calibration This chapter offers you a brief guide to the calibration procedure. Sections include: • Calibration Procedure...

  • Page 46: Chapter 5 Calibration

    Chapter 5 Calibration The PCIE-1744 has been calibrated at the factory for initial use. You are not required to calibrate the PCIE-1744 in normal conditions. However, if calibration is required, the procedure shown in the next pages will show how it is done.

  • Page 47: Figure 5.2:Click The Calibration Button To Launch The Calibration

    Step 2:Select the input range of the channel which you want to calibrate. Step 3:Click the Calibration button to start the calibration process. The Calibration Wizard window will pop up. Note: Each calibration process can calibrate only one channel and one input range at a time. Figure 5.2: Click the Calibration Button to Launch the Calibration Step 4:Follow the instruction of Calibration Wizard to input a correct DC voltage as a reference and click the Next button to proceed to the next...

  • Page 48: Figure 5.5:Offset Calibration Succeeded

    Start button is clicked. When the offset calibration is completed, the Status will indicate Succeeded, then click the Next button to proceed to the next step Figure 5.5: Offset Calibration Succeeded PCIE-1744 User Manual...

  • Page 49: Figure 5.6:Offset Calibration Failed

    Step 6a:Once the Status indicates Failed, please check if both the wiring and the input voltage are correct. When finished checking, click the Start button again to restart the procedure, or click the Cancel button to stop the calibration. Figure 5.6: Offset Calibration Failed Step 7:If the offset calibration is completed, it will proceed to the Gain Calibration.

  • Page 50: Figure 5.9:Gain Calibration Succeeded

    Step 8:Click the Start button to start gain calibration. Note that the Sta- tus will indicate Unknown as default at the beginning. Figure 5.8: The Adjustment Process of Gain Calibration Step 9:When the gain calibration is completed click the Next button to proceed. Figure 5.9: Gain Calibration Succeeded PCIE-1744 User Manual...

  • Page 51: Figure 5.10:Gain Calibration Failed

    Step 9a:Once the Status indicates Failed, please check if both the wiring and the input voltage are correct. When finished checking, click the Start button again to restart the procedure, or click the Cancel button to stop the calibration. Figure 5.10: Gain Calibration Failed Step 10:When the current channel is calibrated, click the Finish button to end the procedure.
  • Page 52 PCIE-1744 User Manual...
  • Page 53 Specifications...

  • Page 54: Appendix A Specifications

    +5 V @ 1 A ; +12 V @ 700mA Max. 0~70° C (32~158° F) Temperature Operating -20 ~ 85° C (-4 ~ 185° F) Storage 5~95%RH, non-condensing (refer to IEC 68-2-3) Relative Humidity CE certified Certification PCIE-1744 User Manual...

  • Page 55: Analog Input

    A.2 Analog Input Channels 4 single-ended analog input channels Resolution 12-bit FIFO Size Max. Sampling Rate 30 MHz Input range and Gain Gain List Range ±5V ±2.5V ±1V ±0.5V Drift Gain Zero ±200 ±100 ±40 ±20 (µV / °C) Gain ±30 ±30 ±30...
  • Page 56 PCIE-1744 User Manual...
  • Page 57 Block Diagram...

  • Page 58: Appendix B Block Diagram

    Appendix B Block Diagram PCIE-1744 User Manual...
  • Page 59 Register Structure & Format...

  • Page 60: Appendix C Register Structure & Format

    The PCIE-1744 is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 2000, XP and Vista operating sys- tems. We advise users to program the PCIE-1744 using the 32-bit DLL driver provided by Advantech to avoid the complexity of low-level pro- gramming by register.

  • Page 61: Table C.1:Pcie-1744 Register Format (Part 1)

    Table C-1 shows the function of each register of the PCIE-1744 or driver and their address relative to the card’s base address. Table C.1: PCIE-1744 register format (Part 1) Base PCIE-1744 Register Format Address + HEX 13 12 11 10 9...

  • Page 62: Table C.2:Pcie-1744 Register Format (Part 2)

    Table C.1: PCIE-1744 register format (Part 1) Ch W Clock Source and Divider Register Eh W Trigger Mode and Source Register TRGF DMA TSE TS2 TS1 TS0 TM2 TM1 TM0 _TCF TRGF DMA TSE TS2 TS1 TS0 TM2 TM1 TM0 _TCF Table C.2: PCIE-1744 register format (Part 2)

  • Page 63: Table C.3:Pcie-1744 Register Format (Part 3)

    Table C.2: PCIE-1744 register format (Part 2) 18h W FIFO 2 Programmable Flag Register PF9 PF8 PF PF5 PF4 PF3 PF2 PF1 R FIFO 2 Programmable Flag Register PF9 PF8 PF PF5 PF4 PF3 PF2 PF1 1Ah W FIFO 3 Programmable Flag Register...
  • Page 64 Table C.3: PCIE-1744 register format (Part 3) 24h W Analog Trigger Threshold voltage Register AT2 AT1 AT0 R Analog Trigger Threshold voltage Register AT2 AT1 AT0 26h W N/A R N/A 28h W Calibration Command Register CG1 CG0 X CD2 CD1 CD0...

  • Page 65: Table C.4:Pcie-1744 Register Format (Part 4)

    Table C.4: PCIE-1744 register format (Part 4) Base PCIE-1744 Register Format Address + HEX 30h W Reset start read channel to CH0 R AD Channel n DATA OV G1 G0 AD1 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0...
  • Page 66 This bit indicates whether the input voltage is over range or not. Read 1 means over range. TRGF Trigger Flag (For about trigger use only) The trigger flag indicates whether a trigger event has happened during A/ D conversion process. PCIE-1744 User Manual...

  • Page 67: Ai Range Control- Write/Read Base+8

    C.4 AI Range Control- Write/Read BASE+8 Table C.6: Register for Analog Input Range Control Base PCIE-1744 Register Format Address + HEX 15 14 12 11 10 9 8 7 AI Range Control Register CH0_ CH0_ Analog Input Range Selector These registers are used to select the analog input range for each channel.

  • Page 68: Clock Source And Divider- Write/Read Base+C

    C.6 Clock Source and Divider- Write/Read BASE+C Table C.8: Register for Clock Source and Divider Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 Ch W Clock Source and Divider Register DIV7: DIV0 Clock Divider When select the internal clock source (60MHz) the clock will pre-divide by the clock divider.

  • Page 69: Trigger Mode And Source- Write/Read Base+E

    TM2 TM1 TM0 TSE TS2 TS1 TS0 TM2 TM1 TM0 TM2: TM0 Trigger Mode selector There are 5 trigger modes for PCIE-1744. Please refer to the operation theorem for more information. Meaning Single value acquisition mode (SW trigger) Pacer acquisition mode...

  • Page 70: Fifo Control- Write Base+10,12

    Trigger not occurred Trigger occurred C.8 FIFO Control- Write BASE+10,12 Table C.10: Register for FIFO Control Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 7 6 5 4 3 2 1 10h W FIFO Control Register...

  • Page 71: Fifo Status- Read Base+10,12

    C.9 FIFO Status- Read BASE+10,12 Table C.11: Register for FIFO Status Base PCIE-1744 Register Format Address + HEX 15 14 13 11 10 7 6 5 10h R FIFO Status Register FIFO FIFO FIFO FIFO1 FIFO FIFO FIFO FIFO0 FIFO...

  • Page 72: Fifo For Programmable Flag - Write/Read

    PF14: PF0 FIFO n Programmable Flag Register (n = 0 ~3) The FIFO on PCIE-1744 is very powerful. It allows user to define the indicate flag in any depth. There are two flags could be defined: FIFO Almost Empty flag and FIFO Almost Full flag. To define these flags must follow the procedure: First write is the Almost Empty flag offset count from the empty.

  • Page 73: Dma Counter - Write/Read Base+1C, Write Base+1E

    C.11 DMA Counter - Write/Read BASE+1C, Write BASE+1E Table C.13: Register for DMA Counter Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 1Ch W DMA Counter Register CN9 CN8 CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0...

  • Page 74: Interrupt Control/Flag- Write/Read Base+20

    R Interrupt Flag INTF3 INTF2 INTF1 INTF0 C.12.1 Interrupt Control Register PCIE-1744 provide 9 sources to generate the interrupt. Write 1 to enable the interrupt, write 0 to disable. The INTE is control the total interrupt. FIFO0_HFFIFO 0 Half Full...

  • Page 75: Clear Interrupt- Write Base+22

    INTF Total Interrupt flag C.13 Clear Interrupt- Write BASE+22 Table C.15: Register for Clear Interrupt Base PCIE-1744 Register Format Address + HEX Clear Interrupt Clear Interrupt Write any value to this address will clear interrupt. It will clear all flags to 0 if there is no any interrupt in coming.

  • Page 76: Analog Trigger Threshold Voltage-Write/Read Base+24

    C.14 Analog Trigger Threshold Voltage-Write/Read BASE+24 Table C.16: Register for Analog Trigger Threshold Voltage Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 24h W Analog Trigger Threshold voltage Register AT7 AT6 AT5 AT4 AT3 AT2 AT1 AT0...

  • Page 77: Calibration Command- Write/Read Base+28

    C.15 Calibration Command- Write/Read BASE+28 Table C.17: Register for Calibration Command Base PCIE-1744 Register Format Address + HEX 15 14 13 28h W Calibration Command Register CG1 CG0 X CM2 CM1 CM0 CD CD3 CD2 CD1 CD0 CG1 CG0 CBU...

  • Page 78: Boardid- Read Base+2C

    C.16 BoardID- Read BASE+2C Table C.18: Register for BoardID Switch Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 2Ch R Board ID BID3 BID2 BID1 BID0 BID3: BID0 BoardID BoardID selector value is from 0 to 15. Please refer to board ID switch setting.

  • Page 79: Ch0

    C.18 AD Channel n DATA- Read BASE+30,32 Table C.20: Register for AD Channel n DATA Base PCIE-1744 Register Format Address + HEX 14 13 12 11 30h R AD Channel n DATA TRGF OV G1 G0 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0...

  • Page 80: Dma Request Selector- Write Base+34

    CH0 data 1 CH3 data 1 CH2 data 1 C.19 DMA Request Selector- Write BASE+34 Table C.21: Register for DMA Request Selector Base PCIE-1744 Register Format Address + HEX 15 14 13 12 11 10 9 34h W DMA Request selector...

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