Write Chain - HP 7936 Support Manual

AGC circuit is gated by Read AGC Gate
(RAGC-H, RAGC-L) from the sampled servo
timing circuit and Write Gate Open (WGO-L),
from the read/write controller. This gating allows
only the data sync field in each sector to deter-
mine the amplitude of the AGC signal. The AGC
circuit output is labeled Automatic Gain Control
(AGC).
5-102. Zero Crossing Detector. The zero-crossing
detector converts the differential analog output of
the video amplifier into TTL-level pulses. Each
data transition, positive or negative, results in a
high-true signal at the detector output. The output
signal, labeled NRZ Data (NRZ-H), is coupled to
the input of the read chain PLL and data
separator stage.
5-103. PLL and Data Separator. The function
of the phase-locked loop (PLL) and data separator
stage is to phase lock a clock source to the read-
back data stream from the disc and separate the
data transitions into timing windows, thus generat-
ing a synchronous clock and a data stream of
VLFM-encoded ones and zeros.
The circuit consists of a voltage-controlled oscil-
lator (VCO) clock source which is locked up to
one of two input signals, depending on the drive
mode of operation. During seeks or writes the
VCO is in a frequency hold (locking) mode, where
it is locked to Differential Write Clock (DWC-L,
OWC-H),
derived from the dedicated servo surface.
During a read, the
veo
is in a phase lock (track-
ing) mode of operation where the
NRZ-H
data
stream from the zero-crossing detector is fed to
the clock source. The changeover between the
two modes is controlled by Read Enable
(RDEN-L)
from the read/write controller IC.
Included in the PLL and data separator are a phase
detector, a frequency detector, and a controlled
clock source. The phase detector compares the
phase of the data source to that of the clock
source and outputs a signal proportional to their
difference. The frequency detector compares the
frequency of the clock source and outputs a signal
proportional to their difference. The controller
clock source advances, maintains, or delays the
phase of the output clock as commanded by a plus,
zero, or minus input signal. The outputs from the
Functional Description
7936 and 7937
PLL and data separator are are labeled Read Data
(RDATA) and Read Clock (ROCLK). Both signals
are fed to the encoder/decoder section of the
read/write controller IC.
5-104. Sampled and Dedicated Servo Amplifiers.
The sampled and dedicated servo amplifiers con-
tained on read/write PCA-A2 are described in the
servo system functional description.
5-105. WRITE CHAIN. Signal Write Gate Open
(WGTO-L)
to the write chain is clocked true by the
falling edge of Start of Sector (SOS-L) when a
write command has previously been entered in the
command register. When
WGTO-L
is low, the
write chain supplies write current on Write
Current (WC) line to the read preamplifier/write
driver ICs in the head-disc assembly.
The read preamplifier/write driver ICs are set in a
write mode of operation by Write Select A, B
(WSA, WSB). A high level (approx 3.5V) on these
lines select the write mode.
Each time a positive edge is seen on the Write
Data
(WDATA)
line from the encoder/decoder, a
D-type flip-flop in the chain steers current into
either the DX or OY line to write data on the disc.
A number of outputs from the write chain are
used in the factory to write the dedicated servo
code. These signals include Servo Write Select
(SWS), Servo Write Current (SWC), and Servo
Head Select (SHS-H). After the drive is manufac-
tured, SHS-H is permanently set low, effectively
limiting the servo head to read-only operation.
5-106. READ/WRITE SYSTEM ERRORS.
Details of the errors detected by the read/write
system are provided in the following paragraphs.
5-107. Unsafe Current in Read/Write ICs. This
error indicates that an unsafe current has been
detected in one of the read preamplifier/write
driver ICs. The error could indicate multiple selec-
tion of the read preamplifier/write driver ICs or
lack of data during a write.
The error can occur any time during the sector.
5-33