HP 7936 Support Manual page 52

Functional Description
7936 and 7937
to the dedicated servo position demodulator and
the
DSRVP
line is coupled to the sector mark
decoder and the dedicated servo timing and PLL
circuitry.
5-38. Position demodulator. The dedicated servo
position demodulator monitors the Dedicated
Servo
(DSRVN)
signal and generates a Dedicated
Position (DPOS) analog signal, which represents
the current position of the servo head relative to
the dedicated servo dibits. This signal is used to
generate the track crossing signal during seeks, and
also to control actuator positioning at the conclu-
sion of a seek.
DPOS
is also used to control head
positioning when servoing in the guard bands.
The DSRVN signal from the dedicated servo
amplifier is input to a dibit peak detector, which
creates a voltage proportional to the amplitude of
the incoming dibits. The output of the peak detec-
tor is fed to a pair of sample-and-hold circuits,
which capture the peak values for the appropriate
dibit pair. The timing of the sample-and-hold cir-
cuits is controlled by two signals, A Sample
(ASMPL)
and B Sample
(BSMPL),
from the dedi-
cated servo timing circuit. These signals ensure
that the proper dibit pair (in-phase or quad) is
sampled at the correct time. A third signal, Dump
(DMP-H), discharges the peak detectors in prepara-
tion for the next sampling cycle.
The outputs of the two sample-and-hold circuits
are input to a position discriminator, which sub-
tracts the two signals. The resultant
DPOS
signal,
which represents the position of the servo head
relative to the dibits being sensed, is used by the
2-bit ADC and track crossing detector during seeks.
DPOS
also controls the position of the actuator at
the conclusion of seeks and when servoing in the
guard bands.
The sample-and-hold circuit outputs are also used
as the input to a level discriminator circuit. This
summing amplifier generates a Dedicated Level
(DLVL) signal proportional to the sum of the two
inputs.
DLVL
represents the level of the servo sig-
nal and is used by the dedicated servo AGC in-
tegrator to generate the proper AGC level.
5-18
5-39. Dedicated Servo Timing And PLL. This
block generates the reference timing signals for
servo and write operations.
The PLL circuit generates the 28.2 MHz
Differential Write Clock (DWC-L, OWC-H) used
when writing data on the disc. The PLL includes a
VCO which, through the use of a phase detector, is
synchronized to DSVRP. In addition, the PLL
generates a Write Clock (WC-H) used by the
sampled servo timing, and also provides the timing
signals for remainder of the dedicated servo
timing. The Lock
(LCK-L)
signal from the servo
controller aids the VCO in locking to the incoming
dibit stream by sweeping the output frequency of
the VCO until lock is achieved.
The dedicated servo timing circuit controls the
operation of the sector mark decoder and the posi-
tion demodulator. The generation of dedicated
servo timing is controlled by three signals from the
servo controller: Guard Band Enable (GBDEN-H),
Quadrature
(QUAD-H),
and Least Significant Bit
(LSB).
The GBOEN-H signal is used to generate the
proper timing signals to allow the sector mark
decoder to search for sector marks (GBOEN-H
inactive) or guard band marks
(GBDEN-H
active).
The primary timing difference between the two
search modes is that when looking for guard band
marks the frequency of ZCLK is doubled. This al-
lows the sector mark decoder to sample each servo
cell twice when looking for missing guard band
dibits; a necessity since each dibit within the guard
band mark represents a discrete state. The two ad-
ditional timing signals (DBGTH, SMCLK) used to
control the operation of the sector mark decoder
are unchanged by the state of
GBOEN-H.
When a
guard band mark is detected, the Guard Band
Detect (GBD) signal from the sector mark decoder
is passed by the dedicated servo timing circuit to
the servo controller.
The state of QUAD-H determines whether the
dedicated servo position demodulator will be con-
figured to process in-phase dibits
(QUAD-H
inac-
tive) or quad dibits (QUAD-H active). In response
to the state of QUAD-H, the dedicated servo timing
circuit generates the proper timing signals for the
position demodulator. These signals, ASMPL,
BSMPL, DMP-H, control the internal sampling