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Functional Description
7936 and 7937
Immediately after the framing word, parallel data
is accepted from the Disc Data Bus (000-007)
lines, as clocked in with Disc Data Strobe
(DDS-H)
from the byte counter. The data, which comes
from
the
DMA/ECC
circuitry in
controller
PCA-A6, is parallel loaded into the shift register.
Once a byte is loaded, the contents of the register
are examined by the pattern detector, which looks
for two-bit and four-bit patterns, as shown in the
VLFM code algorithm.
The output of the pattern detector is coupled to
the bit generator. For every two bits interrogated,
the bit generator outputs three bits of write data
on the
WOATA
line. The write data is RZ encoded.
Every transition is a pulse, which drives a toggle in
the write chain, causing a change in the direction
of the current in the write head.
At a certain point in the sector, Start ECC Field
(SEF-L)
is generated by the byte counter. This sig-
nal changes the data path from the DMA to the
ECC.
Due to the slowness of the ECC IC, the
DMA puts out two dummy bytes after
SEF-L
is
received. These dummy bytes are not written to
the disc.
When a read is performed, Write Clock
(WCLK-L)
is used until the read phase-locked loop is
synchronized. At this time, the clock generator
switches to Read Clock
(ROCLK-L).
After the framing word is recognized, data is
passed through the shift register to the pattern
detector. The resulting serial decoded data is
clocked in bytes to the Disc Data Bus (000-007)
lines with Disc Data Strobe
(DDS-H).
At the ap-
propriate time, the byte detector enables Start ECe
Field
(SEF-L)
line, causing data to be transferred
to the ECe IC.
5-98. HEAD SELECT ENCODER.
Due to
mechanical layout restrictions, the physical head
locations in the head-disc assembly do not match
the addresses required to access them. The head
select encoder maps address register outputs
CHIPO-H
through
CHIP3-H
and
HS1-H, HS2-H
from the read/write controller to select the proper
heads.
The head select encoder outputs are labeled Chip
5-32
Enable
(CEO-L
through
CE3-L)
and Head Select
(HS1-L, HS2-L).
Two additional outputs, labeled Channel
0,1
(CHO-H, CH1-H),
together with
HOS1-H, HOS2-H
are used to address the head gain reference PROM
in the HDA. This circuit is discussed in the servo
system functional description.
5-99. READ CHAIN. Included in the read chain
are a filter and amplifier stage, zero-crossing detec-
tor, AGC circuit, and PLL and data separator
stage. The input to the chain is a stream of
VLFM-encoded pulses from the media, labeled
Read/Write Data
(OX,
OY).
This differential
analog signal is filtered, amplified, and converted
to TTL-level NRZ form before being applied to
the input of the PLL and data separator stage.
From the NRZ data, the PLL and data separator
supplies a stream of ones and zeros, accompanied
by a synchronous clock, to the encoder/decoder
section of the read/write controller IC for further
processing.
5-1 00. Filter and Amplifier. Included in the fil-
ter and amplifier stage are a number of filters, an
AGC amplifier, and a video amplifier.
The filters attenuate signals at frequencies higher
than signal frequencies from the media. The filters
also provide the proper group delay of frequency
to match the read path and provide the proper
timing of the read data.
Automatic gain control of the read data is control-
led by the AGC amplifier. The amplifier amplifies
the Read/Write Data
(OX, OY)
signal by a gain
proportional to the amplitude of the AGC signal
from the AGC circuit.
The video amplifier has a gain of
100
and acts as a
buffer amplifier. The differential analog output
from the amplifier is fed to the input of the zero-
crossing detector and the AGC circuit.
5-101. AGC Circuit. The AGC circuit examines
the amplitude of the video amplifier output and
determines the amount that the gain of the AGC
amplifier has to be increased or decreased in order
to keep the amplitude constant. The action of the
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