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MNEMONIC
ASMP-L
BSMP-L
BSOS-L
CEO-L
thru
CE3-L
CHO-H,
CH1-H
CHIPO-H
thru
CHIP3-H
CLER-L
SIGNAL
A Sample
B Sample
Buffered
Start of
Sector
Chip Enable,
bits 0 thru
3
Chip 0,1
Chip Select,
bits 0 thru
3
Clear
Functional Description
7936 and 7937
Table 5-1. List of Mnemonics (2 of 23)
SOURCE
IJA1
IJA1
liD!
A2
lBII
A2
lBII
A2
[IIA1
DESCRIPTION
DEDICATED SERVO TIMING and PLL
output
to
POSITION
DEMODULA TOR.
ASMP-L
is a timing signal used to sample
dedicated servo bits.
DEDICATED SERVO TIMING and PLL
output
to
POSITION
DEMODULATOR.
BSMP-L
is a timing signal used to sample
dedicated servo bits.
BSOS-L
is an address line to the HEAD
GAIN REFERENCE PROM in HDA A3.
BSOS-L
switches the head gain PROM ad-
dress from read/write heads to servo head.
BSOS-L
is connected to the PROM in HDA
A3 via HDA cable WS.
HEAD SELECT ENCODER outputs which,
together with Head Select bits
HS1-H, HS2-H,
are decoded by the READ PREAMP/WRITE
DRIVER ICs to select the desired read/write
head.
CEO-L
thru
CE3-L
are connected to the
READ PREAMP/WRITE DRIVER ICs in
HDA A3 via HDA cable WS.
HEAD SELECT ENCODER address lines to
the HEAD GAIN REFERENCE PROM in
HDAA3.
CHO-H, CH1-H
are connected to the PROM
in HDA A3 via HDA cable WS.
The four
most significant bits of the
READ/WRITE
CONTROLLER
address
register. Output to the HEAD SELECT
ENCODER.
SERVO CONTROLLER output to FAULT
LATCHES and other circuits in the servo
system.
5-49
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