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PIN
NO.
24
25
26
27
28
29
30
31
32
33
34
35
Troubleshooting and Diagnostics
7936 and 7937
Table 8-3. Servo System Test Connector AU3, Mnemonics (3 of 4)
MNEMONIC
DC OFST
SLVL
GAP-L
VCOV
PHDET
SRVER-L
-12UF
OTEN-H
AMPFLT-L
TFOUT
SSGT-L
TER2
SIGNAL
DC Offset
Sampled
Level
Sector Gap
VCO Voltage
Phase
Detection
Servo
Error
-12 Vdc,
Unfiltered
Off Track
Enable
Amplifier Fault
Transfer
Function
Sampled
Servo
Gate
Timing
Error 2
DESCRIPTION
An external signal can be introduced at
this point to provide a dc offset to signal
PES during track following, to be able to
read/write with no offset.
Addition of A sampled dibits and B
sampled dibits used for sampled servo
AGC.
Complete window for entire sampled ser-
vo code.
Integrated sum of all positive dedicated
servo peaks to control VCO, which
creates read clock.
Dedicated servo positive, scaled for input
to VCO integrator.
Combination of off-track or timing error
1 and 2.
-12 Vdc output of power supply before
the PI filters.
Tie this point low to disable off-track
faults. CAUTION: This means that writ-
ing may occur off track without the disc
dri ve stopping.
This signal goes low if an over velocity,
under voltage, missing 100 KHz clock, or
SPR-L is detected.
This will shut off
amplifier enable.
Output signal used when measuring the
transfer function of the servo system.
Window of A dibits and B dibits of
sampled servo code.
Monitors sync bit to make sure that it
falls within a specified window and is
followed by a specified gap.
8-43
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