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Functional Description
7936 and 7937
MNEMONIC
CLSER-L
CURUS-H
DAGC
DAR
000 thru
DD7
5-50
SIGNAL
Clear Servo
Error
Current
Unsafe
Dedicated
AGC*
DAC
Reference
Disc Data,
bits 0
thru 7
Table 5-1. List of Mnemonics (3 of 23)
SOURCE
[II A1
Ii 1 II
A2
[IIA1
[IIA1
I
A6
II
A2
DESCRIP'I'ION
SERVO CONTROLLER output to FAULT
LATCHES.
CLSER-L
resets a servo controller
error condition.
UNSAFE DETECTOR output which informs
the READ/WRITE CONTROLLER that an
unsafe write condition has been detected in
the· READ PREAMP/ WRITE DRIVER ICs
in the HDA. Recognition of
CURUS-H
by the
READ/WRITE CONTROLLER is limited to
a window starting one microsecond after
Start of Sector
(SOS-L)
goes low and con-
tinuing until
SOS-L
goes high at the end of a
write sector.
Dedicated servo AGC INTEGRATOR analog
voltage output which controls the gain of the
DEDICATED SERVO AGC AMPLIFIER.
DAGC
can be monitored at pin 46 of the ser-
vo test point PCA.
DAGC
is connected to the DEDICA TED
SERVO AGC AMPLIFIER in read/write
PCA-A2. See figure
1iDI.
6.25V reference for the DAC in HDA A3.
(Part of head gain reference circuit.)
DAR
is connected to the DAC in HDA A3
via read/write PCA-A2 and HDA cable WS.
Bidirectional S-bit parallel bus in Disc Data
Bus which carries all data read from or writ-
ten to the media. Data is transferred across
the bus by Disc Data Strobe
(DDS-H).
Transfer takes place during the low state of
Start of Sector
(SOS-L).
Other handshake
lines associated with the bus are Disc Data
Strobe
(DDS-H),
Start ECC Field
(SEF-L),
and
Write Hold Off
(WHO-L).
DDO
thru
DD7
are connected between the
DMA/ECC in controller PCA-A6 and the
READ/WRITE CONTROLLER in read/write
PCA-A2 via connectors A6PI and A2Jl.
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