HP 7936 Support Manual page 86

Functional Description
7936 and 7937
MNEMONIC
OPAO-H
OPCO
thru
OPC7
OPCS-L
5-52
SIGNAL
Data Path
Address Zero
Data Path
Control,
bits 0
thru 7
Data Path
Control
Select
Table 5-1. List of Mnemonics (5 of 23)
SOURCE
Ii1
A6
I
A6
• A2
DESCRIPTION
Data Path Control Bus handshake line from
the DATA PATH CONTROL INTERFACE.
Low state selects the READ/WRITE
CONTROLLER control or status registers;
high state selects the address register.
OPAO-H
is connected to the READ/WRITE
CONTROLLER in read/write PCA-A2 via
connectors A6P I and A2P 1.
Bidirectional parallel 8-bit bus in the Data
Path Control Bus which carries data path
control commands and status information.
Signals which control addressing and hand-
shaking are Data Path Read High Write Low
(OPRHW-L),
Data Path Address Zero
(OPAO-H),
Data Path Control Select
(OPCS-L),
and Data Path Interrupt Request
(OPIRQ-L).
DPCO thru DPC7 are connected between the
DATA PATH CONTROL INTERFACE in
controller PCA-A6 and the READ/WRITE
CONTROLLER in read/write PCA-A2 via
connectors A6P 1 and A2J 1.
Data Path Control Bus handshake line from
DATA PATH CONTROL INTERFACE.
During a read, a low state enables the output
buffers and a high state tristates the output
buffers. During a microprocessor write, data
is strobed into the internal registers on the
rising edge.
OPCS-L
is connected to the READ/WRITE
CONTROLLER in read/write PCA-A2 via
connectors A6P 1 and A2J 1.