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Functional Description
7936 and 7937
MNEMONIC
RAGC-H,
RAGC-L
RDATA
RDCLK-H
RDEN-H
REF-L
RLED
5-60
SIGNAL
Read AGC
Gate
Read Data
Read Clock
Read
Enable**
Reference
Red LED
Table 5-1. List of Mnemonics (13 of 23)
SOURCE
ill
A1
IiJII
A2
IiJII
A2
IiJII
A2
Iii
A6
DESCRIPTION
SAMPLED SERVO TIMING
differential
output which defines the time that the read
chain AGC CIRCUIT is active.
RAGCC-H
and
RAGCC-L
are connected to
the read chain AGC Circuit in read/write
PCA-AI. See figure
1iJII.
NRZ data from the read chain PLL and
DATA SEPARATOR. The data is clocked on
the positive-going edge of Read
Clock
(RDCLK-H)
into the encoder/decoder section
of the READ/WRITE CONTROLLER.
Read data clock from the read chain PLL
and DATA SEPARTOR.
RDCLK-H
is input
to the encoder/decoder section
of
the
READ/WRITE CONTROLLER.
An output from the encoder/decoder section
of the READ/WRITE CONTROLLER to the
PLL and DATA SEPARATOR.
RDEN-H
changes the PLL from a frequency mode to a
phase mode when a read begins.
RDEN-H
can be monitored at pin
II
of the
read/write test point PCA.
DEDICATED SERVO TIMING and PLL
output
to
POSITION
DEMODULATOR.
REF-L
is a reference level which gates the
positive dedicated servo pulse level of accep-
tance. Used in the creation of write clock.
LED DRIVER output to red LED in front
panel LED display.
GLED
is connected to LED PCA-A 7 via
read/write
PCA-A2.
power
distribution
PCA-A5. and power supply output cable W4.
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