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MNEMONIC
WC-H
WCLK-H
WCSO,
WCS1
WDATA-H
WGTO-L
Functional Description
7936 and 7937
Table 5-l. List of Mnemonics (22 of 23)
SIGNAL
Write
Clock
Write
Clock
Write
Current
Select 0,1
Write Data**
Write Gate
Open**
SOURCE
ill
A1
iii
A2
iii
A2
iii
A2
iii
A2
DESCRIPTION
DEDICATED SERVO TIMING output to
SAMPLED SERVO TIMING circuit.
WC-H
serves as the timing signal for the SAMPLED
SERVO TIMING logic.
BUFFER
output
to
WRITE
CHAIN.
WCLK-H
is the single-ended version of dif-
ferential Write Clock
DWC-L, DWC-H.
Address
lines
f or
HEAD
GAIN
REFERENCE PROM in HDA A3.
WCSO, WCS1
are connected to the PROM in
HDA A3 via HDA cable WS.
A READ/WRITE CONTROLLER output.
Signal is VLFM-encoded data in NRZ form,
clocked by the write clock supplied by the
servo system.
A
negative
transition
of
WDATA-H
maps to a transition on the mag-
netic media.
WDAT A-H can be monitored at pin 12 of
the read/write test point PCA.
READ/WRITE CONTROLLER output to
WRITE CHAIN.
WGTO-L
is clocked true
(low) by the the falling edge of Start of
Sector
SOS-L
when a write command has
previously
been
entered
into
the
READ/WRITE
CONTROLLER
command
register. When
WGTO-L
is low, write current
is supplied to the write drivers in HDA A3
and write current in the head is toggled each
time a positive edge is seen at Write Data
WDAT A-H. WGTO-L
is normally deactivated
by
the
positive-going
edge
of
SOS-L.
However, it can also be deactivated by the
detection of a
fault
condition by
the
READ/WRITE CONTROLLER.
WGTO-L can be monitored at pin 10 of the
read/write test point PCA.
5-69
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