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MNEMONIC
SGR
SHS-H
SLPES
SLVL
SMCLK
SMDT-H
SIGNAL
Servo
Gain
Reference
Servo Bead
Select
Slew
Position
Error*
Sampled
Level*
Sector
Mark
Clock
Sector
Mark
Detect*
Functional Description
7936 and 7937
Table 5-1. List of Mnemonics (16 of 23)
SOURCE
liD!
A3
liD!
A2
IIA1
IIA1
II A1
IIA1
DESCRIPTION
Analog current from the BDA DAC which
represents the gain of the heads installed in
the drive. Included in the determination of
DAGC
and
SAGC.
SGR
is connected to the AGC REF DEMOD
SWITCH in servo PCA-Al via HDA cable
WB and read/write PCA-A2.
WRITE CHAIN output to SERVO READ
PREAMP/WRITE DRIVER IC.
SHS-H
is set
high to write the dedicated servo code; there-
after is always low.
SHS-H
is connected to the SERVO READ
PREAMP/WRITE DRIVER IC in HDA A3
via HDA cable WB.
Output from SLEW RATE LIMIT switch to
POSITION LOOP COMPENSATION block.
See
iii.
The switch is controlled by
OFTU-L.
SLPES
can be monitored at pin 17 of the
servo test point PCA.
Sampled servo POSITION DEMODULATOR
output to the AGC INTEGRATOR.
SLVL
represents the addition of the sampled servo
code odd and even dibits.
SL VL
can be monitored at pin 25 of the ser-
vo test point PCA.
DEDICATED SERVO TIMING and PLL
output to SECTOR MARK DECODER.
SMCLK
clocks Sector Mark Detect
(SMDT-H)
out of the SECTOR MARK DECODER.
SERVO
MARK
DECODER
output
to
DEDICATED SERVO TIMING and PLL.
SM DT -H
is asserted when the sector mark
decoder detects a sector mark on the dedi-
cated servo.
SMDT-H
can be monitored at pin 14 of the
servo test point PCA.
5-63
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