Related Manuals for Intel BX80605I5760
Summary of Contents for Intel BX80605I5760
- Page 1 ® Intel Core i7-800 and i5-700 Desktop Processor Series Specification Update March 2011 322166-015 Reference Number:...
- Page 2 It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off.
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Page 3: Table Of Contents
Contents Contents Revision History ....................... 5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................14 Errata ..........................17 Specification Changes....................53 Specification Clarifications ................... 54 Documentation Changes ....................55 § Specification Update... - Page 4 Contents Specification Update...
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Page 5: Revision History
Added Errata AAN98-AAN105. October 2009 -003 Added Errata AAN106-AAN109 November 2009 -004 Updated Errata AAN87 and AAN96. December 2009 Updated Processor Identification table to include the Intel® Core™ i7-860S and i5-750S -005 January 2010 processors. -006 Added Erratum AAN110. January 2010 -007 Added Errata AAN111 and AAN112. -
Page 6: Preface
Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual http://www.intel.com/ ® Intel 64 and IA-32 Architectures Software Developer’s Manual design/processor/ Documentation Changes specupdt/252046.htm... - Page 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.
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Page 8: Summary Tables Of Changes
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 9 Errata (Sheet 1 of 5) Steppings Number Status ERRATA AAN1 No Fix The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page AAN2 No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher AAN3...
- Page 10 Errata (Sheet 2 of 5) Steppings Number Status ERRATA Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not AAN27 No Fix Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in AAN28 No Fix Stuck Core Operating Ratio AAN29 No Fix PECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses...
- Page 11 Errata (Sheet 3 of 5) Steppings Number Status ERRATA Processor Forward Progress Mechanism Interacting With Certain MSR/CSR Writes AAN55 No Fix May Cause Unpredictable System Behavior Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores AAN56 No Fix to Local DRAM Correctly EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a AAN57 No Fix...
- Page 12 VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI AAN82 No Fix Blocking Intel® VT-d Receiving Two Identical Interrupt Requests May Corrupt Attributes of AAN83 No Fix Remapped Interrupt or Hang a Subsequent Interrupt-Remap-Cache Invalidation Command...
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Page 13: Specification Changes
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which AAN113 No Fix Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode IOTLB Invalidations Not Completing on Intel ® VT-d Engine for Integrated High AAN114 No Fix Definition Audio... -
Page 14: Identification Information
Identification Information Component Identification via Programming Interface The Intel Core i7-800 and i5-700 desktop processor series stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number 31:28 27:20... - Page 15 Processor Production Top-side Markings (Example) INTEL ©'08 PROC# BRAND SLxxx [COO] SPEED/CACHE/FMB [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 2) Max Intel® Core Frequency Turbo Boost Shared S-Spec Processor Processor Stepping (GHz) / Technology L3 Cache...
- Page 16 ® ® this SKU, Bit 6 of ECX indicates that the processor supports Intel Trusted Execution Technology (Intel TXT) Safer Mode Extension (SMX). For Intel TXT to be operational as a platform feature the processor ® ® ® must also be enabled for Intel...
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Page 17: Errata
Under certain conditions as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 18 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None identified.
- Page 19 accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. Status: For the steppings affected, see the Summary Tables of Changes. AAN6. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a...
- Page 20 ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
- Page 21 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
- Page 22 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
- Page 23 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 24 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software or system.
- Page 25 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround: Software should not disable Thermal Monitor during processor operation.
- Page 26 AAN30. OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error Problem: If a specific type of internal unclassified error is detected, as identified by IA32_MCi_STATUS.MCACOD=0x0405, the IA32_MCi_ STATUS.OVER (overflow) bit [62] may be erroneously set. Implication: The OVER bit of the MCi_STATUS register may be incorrectly set for a specific internal unclassified error.
- Page 27 AAN33. xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode Problem: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic mode, the xAPIC Timer may slip in its synchronization with the external clock. The xAPIC timer may be shortened by up to one xAPIC timer tick.
- Page 28 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
- Page 29 However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially available software/system. Workaround: None identified.
- Page 30 AAN43. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode).
- Page 31 AAN46. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in another machine check bank (IA32_MCi_STATUS).
- Page 32 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially available software. Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
- Page 33 The aliasing of memory regions, a condition necessary for this erratum to occur, ® is documented as being unsupported in the Intel 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
- Page 34 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 35 AAN58. System May Hang if MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL Commands Are Not Issued in Increasing Populated DDR3 Rank Order Problem: ZQCL commands are used during initialization to calibrate DDR3 termination. A ZQCL command can be issued by writing 1 to the MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6, Function 0, Offset 15, bit[15]) field and it targets the DDR3 rank specified in the RANK field (bits[7:5]) of the same register.
- Page 36 AAN61. Memory Intensive Workloads with Core C6 Transitions May Cause System Hang Problem: Under a complex set of internal conditions, a system running a high cache stress and I/ O workload combined with the presence of frequent core C6 transitions may result in a system hang.
- Page 37 Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions ® in a system with Intel Hyper-Threading Technology enabled may cause a machine check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable system behavior. Implication: This erratum may cause a machine check error, system hang or unpredictable system behavior.
- Page 38 Implication: Due to this erratum, updates to segment descriptors may not be preserved. Intel has not observed this erratum with any commercially available software or system. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
- Page 39 Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
- Page 40 Unpredictable PCI Behavior Accessing Non-existent Memory Space Problem: Locked instructions whose memory reference is split across cache line boundaries and are aborted on PCI behind Intel® 5 Series Chipset and Intel® 3400 Series Chipset may cause subsequent PCI writes to be unpredictable. Implication:...
- Page 41 Attributes of Remapped Interrupt or Hang a Subsequent Interrupt- Remap-Cache Invalidation Command Problem: If the Intel® VT-d (Intel® Virtualization Technology for Directed I/O) interrupt- remapping hardware receives two identical back-to-back interrupt requests, then the attributes of the remapped interrupt returned may be corrupted. This interrupt sequence may also hang the system if the software executes a subsequent interrupt- remap-cache invalidation command.
- Page 42 The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an EIST (Enhanced Intel® SpeedStep Technology) transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling.
- Page 43 0, and the use of appropriate temperature smoothing filters in the range -100 to 0 to minimize fan speed fluctuations, if any, due to these errors. Intel does not recommend initiating system shutdown solely based on PECI readings. For systems...
- Page 44 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: • Intel® Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
- Page 45 If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
- Page 46 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 47 In a complex set of internal conditions when the processor exits from Core C6 state, it is possible that an interrupt may be dropped. Implication: Due to this erratum, an interrupt may be dropped. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
- Page 48 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 49 When Intel VT-d engine for integrated High Definition Audio device is enabled and software requests for IOTLB invalidation while audio traffic is active, the request may not complete and may result in a software hang. Intel has not observed this erratum with any commercially available software.
- Page 50 Threading Technology enabled and has not been observed with commercially available software. Implication: Due to this erratum, SMI handlers may not be able to identify the occurrence of I/O SMIs. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAN116.
- Page 51 AAN120. VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Problem: If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, a VM exit should load the IA32_PERF_GLOBAL_CTRL MSR (38FH) from the IA32_PERF_GLOBAL_CTRL field in the guest-state area of the VMCS. Due to this erratum, such a VM exit may instead clear bits 34:32 of the MSR, loading only bits 31:0 from the VMCS.
- Page 52 AAN124. DTS Temperature Data May Be Incorrect On a Return From the Package C6 Low Power State. Problem: The DTS (Digital Thermal Sensor) temperature value may be incorrect for a small period (less than 2ms) after a return from the package C6 low power state. Implication: The DTS temperature data (including temperatures read by Platform Environment Control Interface) may be reported lower than the actual temperature.
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Page 53: Specification Changes
Specification Changes The Specification Changes listed in this section apply to the following documents: ® • Intel Core™ i7-800 and i5-700 Desktop Processor Series Datasheet – Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 54: Specification Clarifications
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: ® • Intel Core™ i7-800 and i5-700 Desktop Processor Series Datasheet – Volumes 1 and 2 ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ®... -
Page 55: Documentation Changes
All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. ® Note: Documentation changes for Intel 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate ®...