Extension To The 3Dnow! Instruction Set; A.6.8 Prescott New Instructions - AMD SimNow Simulator 4.4.4 User Manual

User Manual
Mnemonic
PAVGUSB mmreg1,mmreg2/m64
PF2ID mmreg1,mmreg2/m64
PFACC mmreg1,mmreg2/m64
PFADD mmreg1,mmreg2/m64
PFCMPEQ mmreg1,mmreg2/m64
PFCMPPGE mmreg1,mmreg2/m64
PFCMPGT mmreg1,mmreg2/m64
PFMAX mmreg1,mmreg2/m64
PFMIN mmreg1,mmreg2/m64
PFMUL mmreg1,mmreg2/m64
PFRCP mmreg1,mmreg2/m64
PFRCPIT1 mmreg1,mmreg2/m64
PFRCPIT2 mmreg1,mmreg2/m64
PFRSQIT1 mmreg1,mmreg2/m64
PFRSQRT mmreg1,mmreg2/m64
PFSUB mmreg1,mmreg2/m64
PFSUBR mmreg1,mmreg2/m64
PI2FD mmreg1,mmreg2/m64
PMULHRW mmreg1,mmreg2/m64
PREFETCH/PREFETCHW
A.6.7 Extension to the 3DNow! Instruction Set
This section describes the five new DSP instructions added to the 3DNow! Instruction
set.
Mnemonic
PF2IW mmreg1,mmreg2/m64
PFNACC mmreg1,mmreg2/m64
PFPNACC mmreg1,mmreg2/m64
PI2FW mmreg1,mmreg2/m64
PSWAPD mmreg1,mmreg2/m64
Table 15-11: Extension to 3DNow! Instruction Reference

A.6.8 Prescott New Instructions

Prescott New Instruction technology for the x64 architecture is a set of 13 new
instructions that accelerate performance of Streaming SIMD Extension technology,
Streaming SIMD Extension 2 technology, and x87-FP math capabilities. The new
technology is compatible with existing software and should run correctly, without
modification. The thirteen new instructions are summarized in the following section. For
detailed information on each instruction refer to a complete Instruction Set Reference.
Appendix A
AMD Confidential
Instruction
Opcode
Average
0F 0F /BF
values.
Converts
0F 0F /1D
operand or packed 32-bit integer.
0F 0F /AE Floating-point accumulate.
0F 0F /9E Packed, floating-point addition.
Packed
0F 0F /B0
equal to.
Packed
0F 0F /90
greater than or equal to.
Packed
0F 0F /A0
greater than.
0F 0F /A4 Packed floating-point maximum.
0F 0F /94 Packed floating-point minimum.
Packed
0F 0F /B4
multiplication.
0F 0F /96 Packed floating-point approximation.
Packed
0F 0F /A6
first iteration step.
Packed
0F 0F /B6
second iteration step.
Packed
0F 0F /A7
square root, first iteration step.
Packed
0F 0F /97
square root approximation.
0F 0F /9A Packed, floating-point subtraction.
Packed,
0F 0F /AA
subtraction.
Packed 32-bit integer to floating-
0F 0F /0D
point conversion.
Multiply signed packed 16-bit values
0F 0F /B7 with rounding and store the high 16
bits.
Prefetch processor cache line into
0F 0D
L1 data cache (Dcache).
Table 15-10: 3DNow!™ Instruction Reference
Instruction
Opcode
Packed
0F 0F /1C
word conversion with sign extend.
Packed
0F 0F /8A
accumulate.
Packed
0F 0F /8E
positive-negative accumulate.
Packed 16-bit integer to floating-
0F 0F /0C
point conversion.
0F 0F /BB Packed swap double word.
September 12
Description
of unsigned packed
packed floating-point
floating-point comparison,
floating-point comparison,
floating-point comparison,
floating-point
floating-point reciprocal,
floating-point reciprocal,
floating-point reciprocal,
floating-point reciprocal,
floating-point reverse
Description
floating-point to integer
floating-point negative
floating-point
th
, 2008
Supported
8-bit
Supported
mixed
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