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User Manual
A.6.4
For more information on Virtualization Technology, see AMD Publication #33047,
AMD64 Virtualization Technology.
Mnemonic
CLGI
INVLPGA
MOV reg32,CR8
MOV reg64,CR8
MOV CR8,reg32
MOV CR8,reg64
SKINIT
STGI
VMLOAD
VMCALL
VMRUN
VMSAVE
A.6.5 64-Bit Media Instruction Reference
These instructions described in this section operate on data located in the 64-bit MMX
registers. Most of the instructions operate in parallel on sets of packed elements called
vectors, although some operate on scalars. The instructions define both integer and
floating-point operations, and include the legacy MMX instructions and the AMD
extensions to the MMX instruction set.
Mnemonic
CVTPD2PI mmx,xmm2/m128
CVTPI2PD xmm,mmx/m64
CVTPI2PS mmx,xmm2/m128
A.6.6 3DNow!™ Instruction Set
This chapter describes the 3DNow! Instruction Set that the simulator supports and
simulates. 3DNow! Technology is a group of new instructions that opens the traditional
processing bottlenecks for floating-point-intensive and multimedia applications.
Mnemonic
FEMMS
224
AMD Confidential
Virtualization Instruction Reference
Instruction
Opcode
0F 01 DD
Clear Global Interrupt Flag.
Invalidates
0F 01 DF
virtual page specified in rAX and the
ASID specified in ECX.
Alternate notation for move from CR8 to
F0 20 /r
register.
Alternate notation for move register to
F0 20 /r
CR8.
Alternate notation for move from CR8 to
F0 22 /r
register.
Alternate notation for move register to
F0 22 /r
CR8.
Secure
initialization
0F 01 DE
attestation.
0F 01 DC
Set Global Interrupt Flag.
0F 01 DA
Load State from VMCB.
0F 01 D9
Call VMM.
0F 01 D8
Run Virtual Machine.
0F 01 DB
Save State to VMCB.
Instruction
Opcode
Converts
floating-point
66 0F 2D /r
register or 128-bit memory location to
packed
doubleword
the destination MMX™ register.
Converts two packed doubleword integer
values
in
66 0F 2A /r
memory location to two packed double-
precision floating-point values in the
destination XMM register.
Converts
values
in
0F 2A /r
memory
floating-point
destination XMM register.
Instruction
Opcode
Fast
0F 0E
floating-point state.
Description
the
TLB
mapping
and
jump,
Description
packed
double-precision
values
in
integers
values
a
MMX™
register
or
packed
doubleword
a
MMX™
register
or
location
to
single-precision
values
in
Description
Enter/Exit
of
the
h
September 12
, 2008
Supported
for
the
with
Supported
an
XMM
in
64-bit
integer
64-bit
the
Supported
MMX
or
Appendix A
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