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User Manual
Mnemonic
POP DS
POP ES
POP SS
POP FS
POP GS
POPA
POPAD
POPF
POPFD
POPFQ
PREFETCH mem8
PREFETCHW mem8
PREFETCHNTA mem8
PREFETCHT0 mem8
PREFETCHT1 mem8
PREFETCHT2 mem8
PUSH reg/mem16
PUSH reg/mem32
PUSH reg/mem64
PUSH reg16
PUSH reg32
PUSH reg64
PUSH imm8
PUSH imm16
PUSH imm32
PUSH imm64
PUSH CS
PUSH SS
PUSH DS
PUSH ES
PUSH FS
PUSH GS
PUSHF
PUSHFD
PUSHFQ
RCL reg/mem8,1
RCL reg/mem8,CL
Appendix A
AMD Confidential
Instruction
Opcode
Pop the top of the stack into the DS
1F
register.
Pop the top of the stack into the ES
07
register.
Pop the top of the stack into the SS
17
register.
Pop the top of the stack into the FS
0F A1
register.
Pop the top of the stack into the GS
0F A9
register.
Pop the DI, SI, BP, SP, BX, DX, CX,
61
and AX registers.
Pop the EDI, ESI, EBP, ESP, EBX, EDX,
61
ECX, and EAX registers.
Pop a word from the stack into the
9D
FLAGS register.
Pop a doubleword from the stack into
9D
the EFLAGS register.
Pop a quadword from the stack into
9D
the RFLAGS register.
Prefetch processor cache line into L1
0F 0D /0
data cache.
Prefetch processor cache line into L1
0F 0D /1
data cache and mark it modified.
Move
data
0F 18 /0
using the NTA reference.
Move
data
0F 18 /1
using the T0 reference.
Move
data
0F 18 /2
using the T1 reference.
Move
data
0F 18 /3
using the T2 reference.
Push
FF /6
register or memory operand onto the
stack.
Push
FF /6
register or memory operand onto the
stack.
Push
FF /6
register or memory operand onto the
stack.
Push
50 +rw
register onto the stack.
Push
50 +rd
register onto the stack.
Push
50 +rq
register onto the stack.
Push an 8-bit immediate value (sign-
6A
extended to 16, 32, or 64 bits) onto
the stack.
Push a 16-=bit immediate value onto
68
the stack.
Push
68
register onto the stack.
Push
68
register onto the stack.
0E
Push the CS selector onto the stack.
16
Push the SS selector onto the stack.
1E
Push the DS selector onto the stack.
06
Push the ES selector onto the stack.
0F A0
Push the FS selector onto the stack.
0F A8
Push the GS selector onto the stack.
9C
Push the FLAGS word onto the stack.
9C
Push the EFLAGS word onto the stack.
9C
Push the RFLAGS word onto the stack.
Rotate the 9 bits consisting of the
D0 /2
carry flag and an 8-bit register or
memory location left 1 bit.
Rotate the 9 bits consisting of the
carry flag and an 8-bit register or
D2 /2
memory location left the number of
bits specified in the CL register.
September 12
Description
closer
to
the
processor
closer
to
the
processor
closer
to
the
processor
closer
to
the
processor
the
contents
of
a
the
contents
of
a
the
contents
of
a
the
contents
of
a
the
contents
of
a
the
contents
of
a
the
contents
of
a
the
contents
of
a
th
, 2008
Supported
16-bit
32-bit
64-bit
16-bit
32-bit
64-bit
32-bit
64-bit
209
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