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User Manual
Mnemonic
LAR reg64,reg/mem16
LGDT mem16:32
LGDT mem16:64
LIDT mem16:32
LIDT mem16:64
LLDT reg/mem16
LMSW reg/mem16
LSL reg16,reg/mem16
LSL reg32,reg/mem16
LSL reg64,reg/mem16
LTR reg/mem16
MOV CRn,reg32
MOV CRn,reg64
MOV reg32,CRn
MOV reg64,CRn
MOV DRn,reg32
MOV DRn,reg64
MOV reg32,DRn
MOV reg64,DRn
RDMSR
RDPMC
RDTSC
RSM
SGDT mem16:32
SGDT mem16:64
SIDT mem16:32
SIDT mem16:64
SLDT reg16
SLDT reg32
SLDT reg64
SLDT mem16
SMSW reg16
SMSW reg32
222
AMD Confidential
Instruction
Opcode
Reads the GDT/LDT descriptor referenced by
the
16-bit
0F 02 /r
attributes
result in the 64-bit destination register.
Loads mem16:32 into the global descriptor
0F 01 /2
table register.
Loads mem16:64 into the global descriptor
0F 01 /2
table register.
Loads mem16:32 into the interrupt descriptor
0F 01 /3
table register.
Loads mem16:64 into the interrupt descriptor
0F 01 /3
table register.
Load the 16-bit segment selector into the
0F 00 /2
local descriptor table register and load the
LDT descriptor from the GDT.
Loads the lower 4 bits of the source into
0F 01 /6
the lower 4 bits of CR0.
Loads a 16-bit general-purpose register with
0F 03 /r
the segment limit or a selector specified in
a 16-bit memory or register operand.
Loads a 32-bit general-purpose register with
0F 03 /r
the segment limit or a selector specified in
a 16-bit memory or register operand.
Loads a 64-bit general-purpose register with
0F 03 /r
the segment limit or a selector specified in
a 16-bit memory or register operand.
Load the 16-bit segment selector into the
0F 00 /3
task register and load the TSS descriptor
from the GDT.
Move the contents of a 32-bit register to
0F 22 /r
CRn.
Move the contents of a 64-bit register to
0F 22 /r
CRn.
Move
the
0F 20 /r
register.
Move
the
0F 20 /r
register.
Move the contents of a 32-bit register to
0F 21 /r
DRn.
Move the contents of a 64-bit register to
0F 21 /r
DRn.
Move
the
0F 23 /r
register.
Move
the
0F 23 /r
register.
0F 32
Copy MSR specified by ECX into EDX:EAX.
Copy
the
0F 33
specified by ECX into EDX:EAX.
0F 31
Copy the time-stamp counter into EDX:EAX.
0F AA
Resume operation of an interrupted program.
Store global descriptor table register to
0F 01 /0
memory.
Store global descriptor table register to
0F 01 /0
memory.
Store interrupt descriptor table register to
0F 01 /1
memory.
Store interrupt descriptor table register to
0F 01 /1
memory.
Store the segment selector from the local
0F 00 /0
descriptor
register.
Store the segment selector from the local
0F 00 /0
descriptor
register.
Store the segment selector from the local
0F 00 /0
descriptor
register.
Store the segment selector from the local
0F 00 /0
descriptor table register to a 16-bit memory
location.
Store the low 16 bits of CR0 to a 16-bit
0F 01 /4
register.
Store the low 32 bits of CR0 to a 32-bit
0F 01 /4
register.
Description
source
operand,
with
00FFFF00h
and
contents
of
CRn
to
contents
of
CRn
to
contents
of
DRn
to
contents
of
DRn
to
performance
monitor
table
register
to
table
register
to
table
register
to
h
September 12
, 2008
Supported
masks
the
saves
the
a
32-bit
a
64-bit
a
32-bit
a
64-bit
counter
a
16-bit
a
32-bit
a
64-bit
Appendix A
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