Table of Contents
Advertisement
User Manual
Mnemonic
JMP rel16off
JMP rel32off
JMP reg/mem16
JMP reg/mem32
JMP reg/mem64
JMP FAR pntr16:16
JMP FAR pntr16:32
JMP FAR mem16:16
JMP FAR mem16:32
LAHF
LDS reg16,mem16:16
LDS reg32,mem16:32
LES reg16,mem16:16
LES reg32,mem16:32
LFS reg16,mem16:16
LFS reg32,mem16:32
LGS reg16,mem16:16
LGS reg32,mem16:32
LSS reg16,mem16:16
LSS reg32,mem16:32
LEA reg16,mem
LEA reg32,mem
LEA reg64,mem
LEAVE
LEAVE
LEAVE
LFENCE
LODS mem8
LODS mem16
LODS mem32
LODS mem64
LODSB
LODSW
LODSD
LODSQ
LOOP rel8off
204
AMD Confidential
Instruction
Opcode
Short jump with the target specified
E9 cw
by a 16-bit signed displacement.
Short jump with the target specified
E9 cd
by a 32-bit signed displacement.
Near jump with the target specified
FF /4
reg/mem16.
Near jump with the target specified
FF /4
reg/mem32.
Near jump with the target specified
FF /4
reg/mem64.
Far
jump
EA cd
specified by a far pointer contained
in the instruction.
Far
jump
EA cp
specified by a far pointer contained
in the instruction.
Far jump indirect, with the target
FF /5
specified by a far pointer in memory.
Far jump indirect, with the target
FF /5
specified by a far pointer in memory.
Load the SF, ZF, AF, PF, and CF flags
9F
into the AH register.
Load DS:reg16 with a far pointer from
C5 /r
memory.
Load DS:reg32 with a far pointer from
C5 /r
memory.
Load ES:reg16 with a far pointer from
C4 /r
memory.
Load ES:reg32 with a far pointer from
C4 /r
memory.
Load FS:reg16 with a far pointer from
0F B4 /r
memory.
Load FS:reg32 with a far pointer from
0F B4 /r
memory.
Load GS:reg16 with a far pointer from
0F B5 /r
memory.
Load GS:reg32 with a far pointer from
0F B5 /r
memory.
Load SS:reg16 with a far pointer from
0F B2 /r
memory.
Load SS:reg32 with a far pointer from
0F B2 /r
memory.
Store effective address in a 16-bit
8D /r
register.
Store effective address in a 32-bit
8D /r
register.
Store effective address in a 64-bit
8D /r
register.
Set the stack pointer SP to the value
C9
in the BP register and pop BP.
Set
the
C9
value in the EBP register and pop
EBP.
Set
the
C9
value in the RBP register and pop
RBP.
Force strong ordering of (serialize)
0F AE E8
load operations.
Load byte at DS:rSI into AL and then
AC
increment or decrement rSI.
Load word at DS:rSI into AX and then
AD
increment or decrement rSI.
Load doubleword at DS:rSI into EAX
AD
and then increment or decrement rSI.
Load quadword at DS:rSI into RAX and
AD
then increment or decrement rSI.
Load byte at DS:rSI into AL and then
AC
increment or decrement rSI.
Load word at DS:rSI into AX and then
AD
increment or decrement rSI.
Load doubleword at DS:rSI into EAX
AD
and then increment or decrement rSI.
Load quadword at DS:rSI into RAX and
AD
then increment or decrement rSI.
Decrement rCX and then jump short if
E2 cb
rCX is not 0.
September 12
Description
direct,
with
the
target
direct,
with
the
target
stack
pointer
ESP
to
stack
pointer
RSP
to
h
, 2008
Supported
the
the
Appendix A
Advertisement
Table of Contents
