Int - Interrupt To Vector; Iret - Return From Interrupt; A.6.3.1 Int – Interrupt To Vector; A.6.3.2 Iret – Return From Interrupt - AMD SimNow Simulator 4.4.4 User Manual

User Manual
Mnemonic
SMSW reg64
SMSW mem16
STI
STR reg16
STR reg32
STR reg64
STR mem16
SWAPGS
SYSCALL
SYSENTER
SYSEXIT
SYSRET
UD2
VERR reg/mem16
VERW
WBINVD
WRMSR
A.6.3.1 INT – Interrupt to Vector
Opcode Instruction
CD INT imm8
CC INT 3
 Interrupt to task-gate is not implemented. An attempt to execute an interrupt to
task-gate results in a „FeatureNotImplemented‟ exception and the simulation will
be stopped.
 When delivering an exception in an attempt to deliver a hardware interrupt the
simulation will not push the resume-flag (RF) onto the stack.
 Always clears VM, NT, TF, and RF bits in rFLAGS.
A.6.3.2 IRET – Return from Interrupt
Opcode Instruction
IRET, IRETD,
CF
IRETQ
The simulator does not support nested task-switching using the rFLAGS nested-task bit
(NT) and the TSS back-link field. An interrupt return (IRET) to the previous task (nested-
task) will result in a „FeatureNotImplemented‟ exception and the simulation will be
stopped.
Appendix A
AMD Confidential
Instruction
Opcode
Store the entire 64 bits of CR0 to a 64-bit
0F 01 /4
register.
0F 01 /4 Store the low 16 bits of CR0 to memory.
FB Set interrupt flag (IF) to 1.
Store the
0F 00 /1 register
register.
Store the
0F 00 /1 register
register.
Store the
0F 00 /1 register
register.
Store the
0F 00 /1
register to a 16-bit memory location.
0F 01 F8 Exchange GS base with KernelGSBase MSR.
0F 05 Call operating system.
0F 34 Call operating system.
0F 35 Return from operating system.
0F 07 Return from operating system.
0F 08 Raise an invalid opcode exception.
Set the zero flag (ZF) to 1 if the segment
0F 00 /4
selected can be read.
Set the zero flag (ZF) to 1 if the segment
0F 00 /5
selected can be written.
Write modified cache lines to main memory,
0F 09 invalidate
external cache flushes.
0F 30 Write EDX:EAX to the MSR specified by ECX.
Table 15-9: System Instruction Reference
Description
Interrupt to Vector.
Interrupt to Debug Vector.
Description
Return from interrupt
Description
segment selector from
to a 16-bit general-purpose
segment selector from
to a 32-bit general-purpose
segment selector from
to a 64-bit general-purpose
segment selector from
internal caches, and
th
September 12 , 2008
Supported
the task
the task
the task
the task
trigger
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