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Mnemonic
ADDSUBPD xmm1,xmm2/m128
ADDSUBPS xmm1,xmm2/m128
FISTTP m16int
FISTTP m32int
FISTTP m64int
HADDPD xmm1,xmm2/m128
HADDPS xmm1,xmm2/m128
HSUBPD xmm1,xmm2/m128
HSUBPS xmm1,xmm2/m128
LDDQU xmm,m128
MONITOR EAX,ECX,EDX
MOVDDUP xmm1,xmm2/m64
MOVSHDUP xmm1,xmm2/m128
MOVSLDUP xmm1,xmm2/m128
MWAIT EAX,ECX
A.6.8.1 MONITOR – Setup Monitor Address
Opcode
Instruction
0F 01 C8
MONITOR
The simulator does not recognize this instruction. Therefore the simulator generates an
invalid-opcode exception.
1
See Section A.6.8.1, "MONITOR – Setup Monitor Address", on page 206.
2
See Section A.6.8.2, "MWAIT – Monitor Wait", on page 207.
226
AMD Confidential
Instruction
Opcode
Add/Subtract packed double-precision
66 0F D0 /r
floating-point number from XMM2/Mem
to XMM1.
Add/Subtract packed single-precision
F2 0F D0 /r
floating-point number from XMM2/Mem
to XMM1.
Store
DF /1
(truncate) in m16int and pop ST.
Store
DB /1
(truncate) in m32int and pop ST.
Store
DD /1
(truncate) in m16int and pop ST.
Add
66 0F 7C /r
precision
from XMM2/Mem to XMM1.
Add
F2 0F 7C /r
precision
from XMM2/Mem to XMM1.
Subtract horizontally packed double-
66 0F 7D /r
precision
from XMM2/Mem to XMM1.
Subtract horizontally packed single-
F2 0F 7D /r
precision
from XMM2/Mem to XMM1.
Load 128 bits
F2 0F F0 /r
register.
Sets up a linear address range to be
monitored by hardware and activates
0F 01 C8
the
should
caching type.
Move 64 bits representing the lower
double-precision
F2 0F 12 /r
XMM2/Mem
duplicate.
Move
single-precision data elements from
F3 0F 16 /r
XMM2/Mem
duplicate high.
Move
single-precision data elements from
F3 0F 12 /r
XMM2/Mem
duplicate low.
A hint that allows the processor to
stop instruction execution and enter
0F 01 C9
an
optimized state until occurrence of
a class events.
Table 15-12: Prescott New Instruction Reference
Description
Setup Monitor Address.
Description
ST
as
a
signed
ST
as
a
signed
ST
as
a
signed
horizontally
packed
floating-point
horizontally
packed
floating-point
floating-point
floating-point
from Memory to XMM
monitor.
The
address
be
of
a
write-back
data
element
to
XMM1
register
128
bits
representing
to
XMM1
register
128
bits
representing
to
XMM1
register
implementation–dependent
h
September 12
, 2008
Supported
integer
integer
integer
double-
numbers
single-
numbers
numbers
numbers
range
1
memory
from
and
packed
and
packed
and
2
Appendix A
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