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Clock Sharing Across Multiple Cores with RocketIO
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X
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BUFG
userclk2
userclk
(125 MHz)
userclk2
userclk
userclk2
userclk
userclk2
userclk
userclk2
Virtex-4
brefclkp
GT11CLK_MGT
(250MHz)
IPAD
MGTCLKP
IPAD
MGTCLKN
brefclkn
(250MHz)
synclk1
(250MHz)
SYNCLK1OUT
MGT tile
Virtex-4
GT11
RocketIO
(A)
TXOUTCLK1
REFCLK1
TXUSRCLK
'0'
TXUSRCLK2
'0'
RXUSRCLK
RXUSRCLK2
Virtex-4
GT11
RocketIO
(B)
NC
TXOUTCLK1
REFCLK1
TXUSRCLK
'0'
TXUSRCLK2
'0'
RXUSRCLK
RXUSRCLK2
MGT tile
Virtex-4
GT11
RocketIO
(A)
NC
TXOUTCLK1
REFCLK1
TXUSRCLK
'0'
TXUSRCLK2
'0'
RXUSRCLK
RXUSRCLK2
Virtex-4
GT11
RocketIO
(B)
NC
TXOUTCLK1
REFCLK1
TXUSRCLK
'0'
TXUSRCLK2
RXUSRCLK
'0'
RXUSRCLK2
R
89
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