Optional Configuration Vector - Xilinx LogiCORE 1000BASE-X User Manual

Optional Configuration Vector

Register 17: Vendor-specific Standard Selection Register
Table 9-35: Vendor-specific Register: Standard Selection Register (Register 17)
Optional Configuration Vector
If
out of the core. These signals are bundled into the CONFIGURATION_VECTOR signal as
defined in
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
15
Reg 17
Figure 9-5: Dynamic Switching (Register 17)
Bit(s) Name
17.15:1 Reserved Always return 0s
16.0 Standard 0 = Core will perform the
1000BASE-X standard. Registers 0
to 16 will behave as per
"1000BASE-X Standard Using the
Optional Auto-Negotiation"
1= Core will perform the SGMII
standard. Registers 0 to 16 will
behave as per
Using the Optional Auto-
Negotiation".
"MDIO Management Interface"
Table 9-36.
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Description Attributes
Returns 0s
read/write
"SGMII Standard
is omitted, relevant configuration signals are brought
R
1 0
Default Value
000000000000000
Determined by the
basex_or_sgmii
port
151