Xilinx LogiCORE 1000BASE-X User Manual page 72

R
Spartan-3, Spartan-3E and Spartan-3A Devices
The logic described previously for Virtex-II and Virtex-II Pro devices does not meet the
input setup and hold requirements for TBI with Spartan-3, Spartan-3E and Spartan-3A
devices. A DCM must be used on both the pma_rx_clk0 and pma_rx_clk1 clock paths
(see
names and logic match
Phase shifting may then be applied to the DCM to fine-tune the setup and hold times at the
TBI IOB input flip-flops. Fixed phase shift is applied to the DCM using constraints in the
example UCF for the example design. See
GMII" in Chapter 12
component_name _block (Block Level from example design)
Ethernet 1000BASE-X PCS/PMA
or SGMII LogiCORE
Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices
72
Figure 6-3). This is performed by the example design delivered with the core (all signal
Figure
for more information.
pma_rx_clk0
pma_rx_clk1
rx_code_group0[0]
rx_code_group1[0]
www.xilinx.com
Chapter 6: The Ten-Bit Interface
6-3).
"Constraints When Implementing an External
BUFG
DCM
CLKIN
CLK0
FB
pma_rx_clk0_bufg
(62.5 MHz)
BUFG
DCM
CLKIN
CLK0
FB
pma_rx_clk1_bufg
(62.5 MHz) IOB LOGIC
rx_code_group0_reg[0]
Q D
rx_code_group1_reg[0]
Q
D
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
IOB LOGIC
IBUFG
pma_rx_clk0
IPAD
IOB LOGIC
IBUFG
pma_rx_clk1
IPAD
IBUF
rx_code_group[0]
IPAD
rx_code_group_ibuf[0]
UG155 March 24, 2008