Integration Of The 1-Gigabit Ethernet Mac To Provide Sgmii; (Or Dynamic Switching) Functionality; Integrating With The Tri-Mode Ethernet Mac Core; Integration Of The Tri-Mode Ethernet Mac To Provide Sgmii (Or Dynamic Switching) Functionality With Tbi - Xilinx LogiCORE 1000BASE-X User Manual

Integrating with the Tri-Mode Ethernet MAC Core

Features of this configuration include:
•
•
•
Integration of the 1-Gigabit Ethernet MAC to Provide SGMII (or Dynamic
Switching) Functionality
The connections required to provide SGMII functionality are identical to the connections
required for either
TBI"
depending upon the chosen physical interface. The only difference is that the Ethernet
1000BASE-X PCS/PMA or SGMII core is generated with the SGMII or Dynamic switching
option.
Note:
should be used to save device resources. Additionally, when operating at 1 Gbps only, the SGMII
Adaptation Module instantiated from within the block level of the example design is not required and
can optionally be removed.
Integrating with the Tri-Mode Ethernet MAC Core
The 1000BASE-X PCS/PMA or SGMII core can be integrated in a single device with the Tri-
Mode Ethernet MAC core to extend the system functionality to include the MAC sub-layer.
This core provides support for operation at 10 Mbps, 100 Mbps, and 1 Gbps.
A description of the latest available IP update containing the Tri-Mode Ethernet MAC core
and instructions can be found in the Tri-Mode Ethernet MAC product Web page:
www.xilinx.com/systemio/temac/index.htm
Integration of the Tri-Mode Ethernet MAC to Provide SGMII (or Dynamic
Switching) Functionality with TBI
Figure 13-7
the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in SGMII mode with the
TBI) to the Tri-Mode Ethernet MAC core. The following is a description of the functionality.
•
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Direct internal connections are made between the GMII interfaces between the two
cores.
If both cores have been generated with the optional management interface, the MDIO
port can be connected up to that of the 1-Gigabit Ethernet MAC core, allowing the
MAC to access the embedded configuration and status registers of the Ethernet
1000BASE-X PCS/PMA or SGMII core.
Due to the embedded Receiver Elastic Buffer in the GTX transceiver, the entire GMII is
synchronous to a single clock domain. Therefore userclk2 is used as the 125 MHz
reference clock for both cores, and the transmitter and receiver logic of the 1-Gigabit
Ethernet MAC core now operate in the same clock domain.
"Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with
or "Integration of the 1-Gigabit Ethernet MAC Using a RocketIO
When operating at 1 Gbps speed only, the Rx Elastic Buffer internal to the GTP transceiver
Caution!
The Tri-Mode Ethernet MAC should always be configured for full-duplex operation
when used with an SGMII. This constraint is due to the increased latency introduced by the
SGMII logic. Without full-duplex operation, frame collisions could be undetected and the MAC
response will not be timely.
illustrates the connections and clock management logic required to interface
The SGMII Adaptation module, provided in the example design for the Ethernet
1000BASE-X PCS/PMA or SGMII core when generated to the SGMII standard, can be
used to interface the two cores.
www.xilinx.com
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Transceiver",
185