Xilinx LogiCORE 1000BASE-X User Manual page 183

Integrating with the 1-Gigabit Ethernet MAC Core
Features of this configuration include:
•
•
•
Virtex-5 LXT and SXT Devices
Figure 13-4
the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode) to
the 1-Gigabit Ethernet MAC core.
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Direct internal connections are made between the GMII interfaces between the two
cores.
If both cores have been generated with the optional management interface, the MDIO
port can be connected up to that of the 1-Gigabit Ethernet MAC core, allowing the
MAC to access the embedded configuration and status registers of the Ethernet
1000BASE-X PCS/PMA or SGMII core.
Due to the embedded Receiver Elastic Buffer in the MGT, the entire GMII is
synchronous to a single clock domain. Therefore userclk2 is used as the 125 MHz
reference clock for both cores, and the transmitter and receiver logic of the 1-Gigabit
Ethernet MAC core now operate in the same clock domain.
illustrates the connections and clock management logic required to interface
userclk2
(125 MHz)
1-Gigabit Ethernet
MAC
LogiCORE
gtx_clk
gmii_rx_clk
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
mdc
mdio_in
mdio_out
no
mdio_tri
connection
Figure 13-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and
PMA Using a Virtex-5 GTP Transceiver
www.xilinx.com
BUFG
component_name_block
(Block Level from example design)
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
gmii_txd[7:0]
gmii_tx_en
userclk
userclk2
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
RocketIO I/F
mdc
mdio_in
mdio_out
mdio_tri
R
IBUFGDS
brefclkp
IPAD
IPAD
clkin
brefclkn
(125MHz)
Virtex-5
GTP
RocketIO
REFCLKOUT
CLKIN
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
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