Xilinx LogiCORE 1000BASE-X User Manual page 76

R
Method 2
This logic from method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180
degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in
place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the
case. If not, the logic of
pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of
rx_code_group[9:0] must be routed to two separate device pads. The IODELAY
elements shown on
resulted.
Ethernet 1000BASE-X PCS/PMA
or SGMII LogiCORE
rx_code_group0[0]
rx_code_group1[0]
Figure 6-7: Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices
76
Figure 6-7
Figure 6-7
pma_rx_clk0
pma_rx_clk0_bufg
(62.5 MHz)
rx_code_group0_reg[0]
pma_rx_clk1
pma_rx_clk1_bufg
(62.5 MHz)
rx_code_group1_reg[0]
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Chapter 6: The Ten-Bit Interface
illustrates an alternate implementation where both
can be used to compensate for any bus skew that has
BUFG
IBUFG
IODELAY
IOB LOGIC
IBUF
IODELAY
Q D
IOB LOGIC
BUFG
IBUFG
IODELAY
IOB LOGIC
IBUF
IODELAY
Q
D
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
IOB LOGIC
pma_rx_clk0
IPAD
rx_code_group[0]
IPAD
pma_rx_clk1
rx_code_group[0]
IPAD
rx_code_group[0]
IPAD
UG155 March 24, 2008